Page 1 H8S/2633 Series H8S/2633 HD6432633 H8S/2632 HD6432632 H8S/2631 HD6432631 H8S/2633 F-ZTAT™ HD64F2633 Hardware Manual ADE-602-165A Rev. 2.0 4/14/00 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 Use of the H8S/2633 Series enables easy implementation of compact, high-performance systems capable of processing large volumes of data. This manual describes the hardware of the H8S/2633 Series. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Page 4 Mode amended 76 to 78 3.5 Address Map in Each Operating Mode Figure 3-1 Memory Map in Each Operating Mode in the H8S/2633 Note 2 added Figure 3-2 Memory Map in Each Operating Mode in the H8S/2632 Note 2 added...
Page 5 Revisions Page Item (See Manual for Details) 5.3.3 Interrupt Exception Handling Vector Table Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities 8-bit timer channel names amended 5.4.2 Interrupt Control Mode 0 Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 amended Figure 7-30 DACK Output Timing 7.6.1 DDS=1...
Page 6 Revisions Page Item (See Manual for Details) 10.12.3 Pin Functions Table 10-21 Port F Pin Functions PF3 description amended 13.1.2 Block Diagram Figure 13-1 Block Diagram of 8-Bit Timer amended 13.1.3 Pin Configuration Table 13-1 Pin Configuration amended 15.1 Overview Amended 15.1.4 Register Configuration Table 15-2 WDT Registers...
Page 7 Revisions Page Item (See Manual for Details) 18.2.8 DDC Switch Register (DDCSWR) Description of bits 7 to 4 amended Bits 3 to 0 amended and Note 2 added Description of CLR3-0 added 18.3.1 I C Bus Data Format Description amended C Bus Data Formats Figure 18-3 I C Bus Formats)
Page 8 Revisions Page Item (See Manual for Details) 19.4.3 Input Sampling and A/D Conversion Time Conversion time amended Table 19-4 A/D Conversion Time (Single Mode) amended 19.6 Usage Notes Permissible Signal Source Impedance amended 20.1.4 Register Configuration Table 20-2 D/A Converter Registers amended 21.2.1 System Control Register (SYSCR) Description of bit 0...
Page 9 Revisions Page Item (See Manual for Details) 844, 845 23.3.1 Connecting a Crystal Resonator Table 23-2 Damping Resistance Value 25 MHz added Crystal Resonator amended 845, 846 Table 23-3 Crystal Resonator Parameters 25 MHz added Figure 23-5 Points for Attention when Using PLL Oscillation Circuit amended 23.3.2 External Clock Input...
Page 10 Revisions Page Item (See Manual for Details) 906 to 25.3.5 Timing of On-Chip Supporting Modules Table 25-9 Timing of On-Chip Supporting Modules Note added Figure 25-21 PPG Output Timing amended 25.4 A/D Conversion Characteristics Table 25-11 A/D Conversion Characteristics Conditions amended 25.5 D/A Conversion Characteristics Table 25-12 D/A Conversion Characteristics...
Page 11 Contents Section 1 Overview ......................Overview..........................Internal Block Diagram...................... Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions in Each Operating Mode..............1.3.3 Pin Functions ......................14 Section 2 ........................21 Overview..........................21 2.1.1 Features ......................... 21 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU........22 2.1.3 Differences from H8/300 CPU ................
Page 12 2.9.1 Overview....................... 63 2.9.2 On-Chip Memory (ROM, RAM)................63 2.9.3 On-Chip Supporting Module Access Timing ............65 2.9.4 External Address Space Access Timing ............... 66 2.10 Usage Note ......................... 66 2.10.1 TAS Instruction ....................66 Section 3 MCU Operating Modes .................
Page 13 5.1.3 Pin Configuration....................93 5.1.4 Register Configuration..................93 Register Descriptions ......................94 5.2.1 System Control Register (SYSCR)............... 94 5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO) ......95 5.2.3 IRQ Enable Register (IER) ................... 96 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ........
Page 14 6.3.4 Operation in Transitions to Power-Down Modes ..........126 6.3.5 PC Break Operation in Continuous Data Transfer ..........127 6.3.6 When Instruction Execution is Delayed by One State.......... 128 6.3.7 Additional Notes ....................129 Section 7 Bus Controller ....................131 Overview..........................
Page 15 7.5.9 Byte Access Control ..................... 179 7.5.10 Burst Operation..................... 181 7.5.11 Refresh Control..................... 185 DMAC Single Address Mode and DRAM Interface ............189 7.6.1 DDS=1 ........................189 7.6.2 DDS=0 ........................190 Burst ROM Interface......................191 7.7.1 Overview....................... 191 7.7.2 Basic Timing......................191 7.7.3 Wait Control......................
Page 16 8.3.4 DMA Control Register (DMACR) ............... 227 8.3.5 DMA Band Control Register (DMABCR) ............231 Register Descriptions (3) ....................236 8.4.1 DMA Write Enable Register (DMAWER)............236 8.4.2 DMA Terminal Control Register (DMATCR) ............. 238 8.4.3 Module Stop Control Register (MSTPCR)............239 Operation..........................
Page 17 Operation..........................305 9.3.1 Overview....................... 305 9.3.2 Activation Sources....................307 9.3.3 DTC Vector Table ....................308 9.3.4 Location of Register Information in Address Space..........312 9.3.5 Normal Mode......................313 9.3.6 Repeat Mode ......................314 9.3.7 Block Transfer Mode.................... 315 9.3.8 Chain Transfer ...................... 317 9.3.9 Operation Timing....................
Page 18 10.8 Port B ..........................369 10.8.1 Overview....................... 369 10.8.2 Register Configuration..................370 10.8.3 Pin Functions ......................373 10.8.4 MOS Input Pull-Up Function................374 10.9 Port C ..........................375 10.9.1 Overview....................... 375 10.9.2 Register Configuration..................376 10.9.3 Pin Functions for Each Mode ................379 10.9.4 MOS Input Pull-Up Function................
Page 19 11.2.8 Timer Start Register (TSTR) ................441 11.2.9 Timer Synchro Register (TSYR) ................442 11.2.10 Module Stop Control Register A (MSTPCRA)............ 443 11.3 Interface to Bus Master...................... 444 11.3.1 16-Bit Registers ....................444 11.3.2 8-Bit Registers ...................... 444 11.4 Operation..........................446 11.4.1 Overview.......................
Page 20 12.3.5 Inverted Pulse Output ................... 516 12.3.6 Pulse Output Triggered by Input Capture............. 517 12.4 Usage Notes ........................518 Section 13 8-Bit Timers (TMR) ..................521 13.1 Overview..........................521 13.1.1 Features ......................... 521 13.1.2 Block Diagram...................... 522 13.1.3 Pin Configuration....................523 13.1.4 Register Configuration..................
Page 21 14.2.2 PWM D/A Data Registers A and B (DADRA and DADRB) ......551 14.2.3 PWM D/A Control Register (DACR)..............552 14.2.4 Module Stop Control Register B (MSTPCRB) ............ 554 14.3 Bus Master Interface ......................555 14.4 Operation..........................558 Section 15 Watchdog Timer ....................
Page 22 16.2.6 Serial Control Register (SCR) ................594 16.2.7 Serial Status Register (SSR) ................. 598 16.2.8 Bit Rate Register (BRR) ..................602 16.2.9 Smart Card Mode Register (SCMR)..............611 16.2.10 IrDA Control Register (IrCR)................612 16.2.11 Module Stop Control Registers B and C (MSTPCRB, MSTPCRC)....613 16.3 Operation..........................
Page 23 18.2 Register Descriptions ......................696 18.2.1 I C Bus Data Register (ICDR)................696 18.2.2 Slave Address Register (SAR)................699 18.2.3 Second Slave Address Register (SARX).............. 700 18.2.4 I C Bus Mode Register (ICMR)................701 18.2.5 I C Bus Control Register (ICCR)................704 18.2.6 I C Bus Status Register (ICSR) ................
Page 24 Section 20 D/A Converter ....................769 20.1 Overview..........................769 20.1.1 Features ......................... 769 20.1.2 Block Diagram...................... 769 20.1.3 Input and Output Pins ................... 771 20.1.4 Register Configuration..................771 20.2 Register Descriptions ......................772 20.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3)..........772 20.2.2 D/A Control Register 01 and 23 (DACR01 and DACR23)........
Page 25 22.6.2 User Program Mode....................803 22.7 Programming/Erasing Flash Memory................805 22.7.1 Program Mode ...................... 806 22.7.2 Program-Verify Mode ..................807 22.7.3 Erase Mode ......................811 22.7.4 Erase-Verify Mode....................811 22.8 Protection ........................... 813 22.8.1 Hardware Protection ..................... 813 22.8.2 Software Protection ....................814 22.8.3 Error Protection ....................
Page 26 Section 24 Power-Down Modes ..................853 24.1 Overview..........................853 24.1.1 Register Configuration..................857 24.2 Register Descriptions ......................858 24.2.1 Standby Control Register (SBYCR) ..............858 24.2.2 System Clock Control Register (SCKCR)............860 24.2.3 Low-Power Control Register (LPWRCR)............861 24.2.4 Timer Control/Status Register (TCSR) ..............864 24.2.5 Module Stop Control Register (MSTPCR)............
Page 27 25.3.1 Clock Timing ......................889 25.3.2 Control Signal Timing ..................891 25.3.3 Bus Timing ......................893 25.3.4 DMAC Timing...................... 902 25.3.5 Timing of On-Chip Supporting Modules.............. 906 25.4 A/D Conversion Characteristics ..................914 25.5 D/A Conversion Characteristics ..................915 25.6 Flash Memory Characteristics ................... 916 25.7 Usage Note .........................
Page 28 Appendix G Package Dimensions ................. 1154 xviii...
Page 29 Section 1 Overview Overview The H8S/2633 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
Page 30  Powerful bit-manipulation instructions • Two CPU operating modes  Normal mode: 64-kbyte address space (cannot be used in the H8S/2633 Series)  Advanced mode: 16-Mbyte address space • Bus controller Address space divided into 8 areas, with bus specifications settable independently for each area •...
Page 31 Item Specification • Can be activated by internal interrupt or software Data transfer • controller (DTC) Multiple transfers or multiple types of transfer possible for one activation source • Transfer possible in repeat mode, block transfer mode, etc. • Request can be sent to CPU for interrupt that activated DTC •...
Page 32 Output: 4 channels • 73 I/O pins, 16 input-only pins I/O ports • PROM or mask ROM Memory • High-speed static RAM Product Name H8S/2633 256 kbytes 16 kbytes H8S/2632 192 kbytes 12 kbytes H8S/2631 128 kbytes 8 kbytes •...
Page 33 Item Specification Operating modes Four MCU operating modes External Data Bus Operating On-Chip Initial Maximum Mode Mode Description Value Value Advanced On-chip ROM disabled Disabled 16 bits 16 bits expansion mode On-chip ROM disabled Disabled 8 bits 16 bits expansion mode On-chip ROM enabled Enabled 8 bits...
Page 34 P96/AN14/DA2 P72/ TMO0/TEND0/CS6/SYNCI P95/AN13 P71/ TMR23/TMC23/DREQ1/CS5 P94/AN12 P70/TMR01/TMC01/DREQ0/CS4 P93/AN11 P92/AN10 P91/AN9 Port 1 Port 4 P90/AN8 Notes: 1. Applies to the H8S/2633 only. 2. The FWE pin is used only in the flash memory version. Figure 1-1 Internal Block Diagram...
Page 35 Pin Description 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8S/2633 Series. AVCC P36/RxD4 Vref P35/SCK1/SCK4/SCL0/IRQ5 P40/AN0 P34/RxD1/SDA0 P41/AN1 P33/TxD1/SCL1 P42/AN2 P43/AN3 P32/SCK0/SDA1/IRQ4 P44/AN4 PVCC2 P45/AN5 P31/RxD0/IrRxD P46/AN6/DA0 P30/TxD0/IrTxD P47/AN7/DA1 PD7/D15 P90/AN8 PD6/D14 P91/AN9 PD5/D13 P92/AN10 PD4/D12...
Page 36 P34/RxD1/SDA0 P40/AN0 P33/TxD1/SCL1 P41/AN1 P42/AN2 P32/SCK0/SDA1/IRQ4 P43/AN3 PVCC2 P44/AN4 P31/RxD0/IrRxD P45/AN5 P30/TxD0/IrTxD P46/AN6/DA0 PD7/D15 P47/AN7/DA1 PD6/D14 P90/AN8 PD5/D13 P91/AN9 PD4/D12 P92/AN10 PD3/D11 P93/AN11 PD2/D10 P94/AN12 PD1/D9 TOP VIEW P95/AN13 PVCC1 P96/AN14/DA2 (FP-128) PD0/D8 P97/AN15/DA3 AVSS PE7/D7 P70/TMRI01/TMCI01/DREQ0/CS4 PE6/D6 P71/TMRI23/TMCI23/DREQ1/CS5 PE5/D5 P72/TMO0/TEND0/CS6/SYNCI PE4/D4 P73/TMO1/TEND1/CS7...
Page 37 1.3.2 Pin Functions in Each Operating Mode Table 1-2 shows the pin functions of the H8S/2633 Series in each of the operating modes. Table 1-2 Pin Functions in Each Operating Mode Pin No. Pin Name TFP-120 FP-128 Mode 4 Mode 5...
Page 38 Pin No. Pin Name TFP-120 FP-128 Mode 4 Mode 5 Mode 6 Mode 7 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ TCLKA/A22 TCLKA/A22 TCLKA/A22 TCLKA P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ TCLKB/A23 TCLKB/A23 TCLKB/A23 TCLKB P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ IRQ0 IRQ0 IRQ0 IRQ0 — — P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/...
Page 39 Pin No. Pin Name TFP-120 FP-128 Mode 4 Mode 5 Mode 6 Mode 7 P31/RxD0/IrRxD P31/RxD0/IrRxD P31/RxD0/IrRxD P31/RxD0/IrRxD PVCC2 PVCC2 PVCC2 PVCC2 P32/SCK0/SDA1/ P32/SCK0/SDA1/ P32/SCK0/SDA1/ P32/SCK0/SDA1/ IRQ4 IRQ4 IRQ4 IRQ4 P33/TxD1/SCL1 P33/TxD1/SCL1 P33/TxD1/SCL1 P33/TxD1/SCL1 P34/RxD1/SDA0 P34/RxD1/SDA0 P34/RxD1/SDA0 P34/RxD1/SDA0 P35/SCK1/SCK4/ P35/SCK1/SCK4/ P35/SCK1/SCK4/ P35/SCK1/SCK4/ SCL0/IRQ5...
Page 40 Pin No. Pin Name TFP-120 FP-128 Mode 4 Mode 5 Mode 6 Mode 7 OSC2 OSC2 OSC2 OSC2 PVCC1 PVCC1 PVCC1 PVCC1 PF7/ø PF7/ø PF7/ø PF7/ø AS/LCAS AS/LCAS AS/LCAS PF3/LWR/ADTRG/ PF3/LWR/ADTRG/ PF3/ADTRG/IRQ3 IRQ3 IRQ3 PF2/LCAS/WAIT/ PF2/LCAS/WAIT/ PF2/LCAS/WAIT/ BREQO BREQO BREQO PF1/BACK/BUZZ PF1/BACK/BUZZ PF1/BACK/BUZZ...
Page 41 Pin No. Pin Name TFP-120 FP-128 Mode 4 Mode 5 Mode 6 Mode 7 P96/AN14/DA2 P96/AN14/DA2 P96/AN14/DA2 P96/AN14/DA2 P97/AN15/DA3 P97/AN15/DA3 P97/AN15/DA3 P97/AN15/DA3 AVSS AVSS AVSS AVSS P70/TMRI01/TMCI01/ P70/TMRI01/TMCI01/ P70/TMRI01/TMCI01/ P70/TMRI01/TMCI01/ DREQ0/CS4 DREQ0/CS4 DREQ0/CS4 DREQ0 P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ DREQ1/CS5 DREQ1/CS5 DREQ1/CS5 DREQ1 P72/TMO0/TEND0/...
Page 42 1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2633 Series. Table 1-3 Pin Functions Type Symbol Name and Function Power Input Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply.
Page 43 Mode pins: These pins set the operating mode. control The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2633 Series is operating. Operating Mode —...
Page 44 Type Symbol Name and Function Interrupts Input Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. IRQ7 to IRQ0 Input Interrupt request 7 to 0: These pins request a maskable interrupt. Address bus A23 to A0 Output Address bus: These pins output an address.
Page 45 Type Symbol Name and Function DREQ1, DMA controller Input DMA request 1,0: DREQ0 (DMAC) Requests DMAC activation. TEND1, Output DMA transfer completed 1,0: TEND0 Indicates DMAC data transfer end. DACK1, Output DMA transfer acknowledge 1,0: DACK0 DMAC single address transfer acknowledge pin. 16-bit timer- TCLKD to Input...
Page 46 Type Symbol Name and Function 14-bit PWM timer PWM0 to Output PWMX timer output: PWM D/A pulse output pins. (PWMX) PWM3 WDTOVF Watchdog Output Watchdog timer overflows: The counter overflows timer (WDT) signal output pin in watchdog timer mode. BUZZ Output BUZZ output: Output pins for the pulse divided by the watchdog timer.
Page 47 Type Symbol Name and Function A/D converter, AVSS Input Analog circuit ground and reference voltage D/A converter A/D converter and D/A converter ground and reference voltage. Connect to system power supply (0 V). Vref Input A/D converter and D/A converter reference voltage input pin When the A/D converter and D/A converter are not used, this pin should be connected to the system...
Page 48 Section 2 CPU Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control.
Page 49  32 ÷ 16-bit register-register divide : 800 ns • Two CPU operating modes  Normal mode*  Advanced mode Note: * Not available in the H8S/2633 Series. • Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Page 50  Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.  Advanced mode supports a maximum 16-Mbyte address space. Note: * Not available in the H8S/2633 Series. • Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
Page 51 Note: * Not available in the H8S/2633 Series. Figure 2-1 CPU Operating Modes (1) Normal Mode (Not Available in the H8S/2633 Series) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed.
Page 52 Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2-2).
Page 53 Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is not pushed onto the stack.
Page 54 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). For details of the exception vector table, see section 4, Exception Handling.
Page 55 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When EXR is invalid, it is not pushed onto the stack.
Page 56 (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2633 Series H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Note: * Not available in the H8S/2633 Series. Figure 2-6 Memory Map...
Page 57 Interrupt mask bits Overflow flag CCR: Condition-code register Carry flag Interrupt mask bit MAC: Multiply-accumulate register User bit or interrupt mask bit* Note: * Cannot be used as an interrupt mask bit in the H8S/2633 Series. Figure 2-7 CPU Registers...
Page 58 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Page 59 General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. Free area SP (ER7) Stack area Figure 2-9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),...
Page 60 Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 61 Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 62 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 63 Data Type Register Number Data Format Word data Word data Longword data Legend ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-10 General Register Data Formats (cont)
Page 64 2.5.2 Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 65 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Not available in the H8S/2633 Series.
Page 66 2.6.2 Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes...
Page 68 2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs)
Page 69 Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in the H8S/2633 Series. MOVTPE Cannot be used in the H8S/2633 Series. @SP+ → Rn Pops a register from the stack.
Page 70 Type Instruction Size* Function Rd × Rs → Rd Arithmetic MULXU operations Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd × Rs → Rd MULXS Performs signed multiplication on data in two general registers: either 8 bits ×...
Page 71 Type Instruction Size* Function 0 → MAC Arithmetic CLRMAC — operations Clears the multiply-accumulate register to zero. Rs → MAC, MAC → Rd LDMAC STMAC Transfers data between a general register and a multiply-accumulate register. Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Logic B/W/L operations...
Page 72 Type Instruction Size* Function ¬ (<bit-No.> of <EAd>) → Z Bit- BTST manipulation Tests a specified bit in a general register or memory instructions operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 73 Type Instruction Size* Function C → (<bit-No.> of <EAd>) Bit- manipulation Transfers the carry flag value to a specified bit in a instructions general register or memory operand. ¬ C → (<bit-No.> of <EAd>) BIST Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand.
Page 74 Type Instruction Size* Function (EAs) → CCR, (EAs) → EXR System control instructions Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR →...
Page 75 2.6.4 Basic Instruction Formats The H8S/2633 Series instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand.
Page 76 Figure 2-12 shows examples of instruction formats. (1) Operation field only NOP, RTS, etc. (2) Operation field and register fields ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field EA (disp) BRA d:16, etc...
Page 77 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
Page 78 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction 24 bits (@aa:24) address Note: * Not available in the H8S/2633 Series.
Page 79 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the H8S/2633 Series.
Page 80 (a) Normal Mode * (b) Advanced Mode Note: * Not available in the H8S/2633 Series. Figure 2-13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address.
Page 81 Table 2-6 Effective Address Calculation...
Page 84 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
Page 85 End of bus request Bus request Program execution state Bus-released state Sleep mode External interrupt request Software standby mode Exception handling state MRES= High RES= High STBY= High, RES= Low Power-on reset state * Hardware standby mode* Manual reset state * Reset state *1 Power-down state* Notes: 1.
Page 86 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions.
Page 87 (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES pin goes high again, reset exception handling starts. After the reset state has been entered by driving the MRES pin low while manual resets are enabled by the MRESE bit, reset exception handling starts when MRES pin is driven high again.
Page 88 (b) Interrupt control mode 2 Advanced mode Reserved (24 bits) (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Notes: 1. Ignored when returning. 2. Not available in the H8S/2633 Series. Figure 2-16 Stack Structure after Exception Handling (Examples)
Page 89 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU are DMA controller (DMAC) and data transfer controller (DTC).
Page 90 Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states.
Page 91 Bus cycle ø Address bus Unchanged High High HWR, LWR High Data bus High-impedance state Figure 2-18 Pin States during On-Chip Memory Access...
Page 92 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access timing for the on-chip supporting modules. Figure 2-20 shows the pin states. Bus cycle ø...
Page 93 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or...
Page 94 3.1.1 Operating Mode Selection The H8S/2633 Series has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0).
Page 95 The H8S/2633 Series can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration...
Page 96 3.2.2 System Control Register (SYSCR) MACS — INTM1 INTM0 NMIEG MRESE — RAME Initial value — — SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI, enables or disenables MRES pin input, and enables or disenables on-chip RAM.
Page 97 Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG Description An interrupt is requested at the falling edge of NMI input (Initial value) An interrupt is requested at the rising edge of NMI input Bit 2—Manual Reset Selection Bit (MRESE): Enables or disenables manual reset input.
Page 98 3.2.3 Pin Function Control Register (PFCR) CSS07 CSS36 BUZZE LCASS Initial value PFCR is an 8-bit readable-writable register that carries out CS selection control for PG4 and PG1 pins, LCAS selection control for PF2 and PF6 pins, and address output control during extension modes with ROM.
Page 99 Bit 5—BUZZ Output Enable (BUZZE): Disenables/enables BUZZ output of PF1 pin. Input clock of WDT1 selected by PSS, CKS2 to CKS0 bits is output as a BUZZ signal. Bit 5 BUZZE Description Functions as PF1 input pin (Initial value) Functions as BUZZ output pin Bit 4—LCAS Output Pin Selection Bit (LCASS): Selects the LCAS signal output pin.
Page 100 Bit 3 Bit 2 Bit 1 Bit 0 Description A8–A23 address output disabled (Initial value*) A8 address output enabled; A9–A23 address output disabled A8, A9 address output enabled; A10–A23 address output disabled A8–A10 address output enabled; A11–A23 address output disabled A8–A11 address output enabled;...
Page 101 Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals.
Page 102 *: After reset Address Map in Each Operating Mode A address map of the H8S/2633 is shown in figure 3.1, and a address map of the H8S/2632 in figure 3-2. The address space is 16 kbytes in modes 4 to 7 (advanced modes).
Page 103 H'FFFFFF H'FFFFFF H'FFFFFF Notes: External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Area H'FFF800 to H'FFFDAB is reserved, and must not be accessed. Figure 3-1 Memory Map in Each Operating Mode in the H8S/2633...
Page 104 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip mode) with on-chip ROM disabled) with on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM External address space H'02FFFF H'030000 Reserved area H'040000 External address space H'FFB000...
Page 105 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip mode) with on-chip ROM disabled) with on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'01FFFF H'020000 External address space Reserved area H'040000 External address space H'FFB000...
Page 106 Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, direct transition, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 107 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3.
Page 108 Table 4-2 Exception Vector Table Vector Address* Exception Source Vector Number Advanced Mode Power-on reset H'0000 to H'0003 Manual reset* H'0004 to H'0007 Reserved for system use H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 Trace H'0014 to H'0017 Direct transition* H'0018 to H'001B External interrupt...
Page 109 Reset 4.2.1 Overview A reset has the highest exception handling priority. There are two kinds of reset: a power-on reset executed via the RES pin, and a manual reset executed via the MRES pin. When the RES or MRES pin* goes low, currently executing processing is halted and the chip enters the reset state.
Page 110 Table 4-3 Types of Reset Type Conditions for Transition to Reset Internal State MRES Built-in vicinity module Power-on reset * Initialization Initialization Manual reset High Initialization Initialization except for bus controller and I/O port *: Don't Care 4.2.3 Reset Sequence This LSI enters reset state when the RES pin or MRES pin goes low.
Page 111 Vector Internal Prefetch of first program fetch processing instruction Ø RES, MRES Address bus HWR, LWR High D15 to D0 (1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000*, (3) = H'000002; when manual reset, (1)= H'000004, (3)= H'000006) (2) (4) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction...
Page 112 Prefetch of Vector Internal first program fetch processing instruction ø RES, MRES Internal address bus Internal read signal Internal write High signal Internal data (1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction...
Page 113 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction.
Page 114 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 72 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), DMA controller (DMAC), PC break controller (PBC), A/D converter, and I bus interface (IIC).
Page 115 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code.
Page 116 (16 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return. Figure 4-5 (1) Stack Status after Exception Handling (Normal Modes: Not Available in the H8S/2633 Series) Reserved* (24bits) (24bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return.
Page 117 Notes on Use of the Stack When accessing word data or longword data, the H8S/2633 Series assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W...
Page 118 Overview 5.1.1 Features The H8S/2633 Series controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR).
Page 119 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority ISCR determination Internal interrupt request I2 to I0 SWDTEND to TEI4 Interrupt controller...
Page 120 5.1.3 Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Interrupt Controller Pins Name Symbol Function Nonmaskable interrupt Input Nonmaskable external interrupt; rising or falling edge can be selected IRQ7 to IRQ0 Input External interrupt Maskable external interrupts; rising, falling, or requests 7 to 0 both edges, or level sensing, can be selected 5.1.4...
Page 121 Register Descriptions 5.2.1 System Control Register (SYSCR) MACS — INTM1 INTM0 NMIEG MRESE — RAME Initial value — — SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR).
Page 122 5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO) — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Initial value — — The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI.
Page 123 As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.
Page 124 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
Page 125 5.2.5 IRQ Status Register (ISR) IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests.
Page 126 There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ7 to IRQ0 can be used to restore the H8S/2633 Series from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
Page 127 Figure 5-3 shows the timing of setting IRQnF. ø IRQn input pin IRQnF Figure 5-3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output.
Page 128 Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority External H'001C High IRQ0 H'0040 IPRA6 to 4 IRQ1 H'0044 IPRA2 to 0 IRQ2 H'0048 IPRB6 to 4 IRQ3 H'004C IRQ4...
Page 129 Vector Address* Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority TGI1A (TGR1A input H'00A0 IPRF2 to 0 High capture/compare match) channel 1 TGI1B (TGR1B input H'00A4 capture/compare match) TCI1V (overflow 1) H'00A8 TCI1U (underflow 1) H'00AC TGI2A (TGR2A input H'00B0 IPRG6 to 4 capture/compare match)
Page 130 Vector Address* Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority CMIA0 (compare match A0) 8-bit timer H'0100 IPRI6 to 4 High CMIB0 (compare match B0) channel 0 H'0104 OVI0 (overflow 0) H'0108 Reserved — H'010C CMIA1 (compare match A1) 8-bit timer H'0110 IPRI2 to 0...
Page 131 Vector Address* Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority CMIA0 (compare match A2) 8 bit timer H'0170 IPRL6 to 4 High CMIB0 (compare match B2) channel 2 H'0174 OVI0 (overflow 2) H'0178 Reserved — H'017C CMIA1 (compare match A3) 8 bit timer H'0180 CMIB1 (compare match B3)
Page 132 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2633 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
Page 133 Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 Interrupt acceptance control Default priority Interrupt source Vector number determination 8-level mask control I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.
Page 134 (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level.
Page 135 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1.
Page 136 Program execution status Interrupt generated? Hold pending IRQ0 IRQ1 TEI4 Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0...
Page 137 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
Page 138 Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 Level 1 interrupt? or below? Mask level 5 or below? Mask level 0? Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in...
Page 139 5.4.4 Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5-7 Interrupt Exception Handling...
Page 140 5.4.5 Interrupt Response Times The H8S/2633 Series is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high- speed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine.
Page 141 Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus Internal 2-State 3-State 2-State 3-State Symbol Memory Access Access Access Access Instruction fetch 6+2m Branch address read Stack manipulation Legend : Number of wait states in an external device access.
Page 142 CMIA exception handling TCR write cycle by CPU ø Internal TCR address address bus Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5-8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
Page 143 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle.
Page 144 DMAC Interrupt DTC activation request request vector Selection number circuit Select interrupt signal Control logic Clear signal DTCER Interrupt source On-chip Clear signal clear signal supporting module DTVECR SWDTE CPU interrupt clear signal request vector number Determination of priority I, I2 to I0 Interrupt controller Figure 5-9 Interrupt Control for DTC and DMAC 5.6.3...
Page 145 (2) Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See 8.6 Interrupts and 9.3.3 DTC Vector Table for the respective priority. (3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling.
Page 146 Section 6 PC Break Controller (PBC) Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC: instruction fetch, data read, data write, and data read/write.
Page 147 6.1.2 Block Diagram Figure 6-1 shows a block diagram of the PC break controller. BARA BCRA Mask control Control Comparator logic Match signal Internal address PC break interrupt Access status Control Comparator logic Match signal Mask control BARB BCRB Figure 6-1 Block Diagram of PC Break Controller...
Page 148 6.1.3 Register Configuration Table 6-1 shows the PC break controller registers. Table 6-1 PC Break Controller Registers Initial Value Power-On Manual Name Abbreviation Reset Reset Address* Break address register A BARA H'XX000000 Retained H'FE00 Break address register B BARB H'XX000000 Retained H'FE04 Break control register A BCRA...
Page 149 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) CMFA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA Initial value : R/(W)* Note: * Only 0 can be written, for flag clearing.
Page 150 Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2–BAMRA0): These bits specify which bits of the break address (BAA23–BAA0) set in BARA are to be masked. Bit 5 Bit 4 Bit 3 BAMRA2 BAMRA1 BAMRA0 Description All BARA bits are unmasked and included in break conditions (Initial value) BAA0 (lowest bit) is masked, and not included in break conditions...
Page 151 6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.2.5 Module Stop Control Register C (MSTPCRC) MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
Page 152 Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in sections 6.3.1 and 6.3.2, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch (1) Initial settings  Set the break address in BARA. For a PC break caused by an instruction fetch, set the address of the first instruction byte as the break address.
Page 153 (2) Satisfaction of break condition  After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. (3) Interrupt handling  After priority determination by the interrupt controller, PC break interrupt exception handling is started.
Page 154 After execution of the SLEEP instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (C)). (4) When the SLEEP instruction causes a transition to software standby mode or watch mode: After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break interrupt handling is not executed.
Page 155 6.3.6 When Instruction Execution is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. (1) When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in on- chip ROM or RAM is always delayed by one state.
Page 156 6.3.7 Additional Notes (1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address.
Page 157 Section 7 Bus Controller Overview The H8S/2633 Series has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
Page 158 • Idle cycle insertion  An idle cycle can be inserted in case of an external read cycle between different areas  An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle •...
Page 159 7.1.2 Block Diagram Figure 7-1 shows a block diagram of the bus controller. CS0 to CS7 Internal Area decoder address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK Internal control controller signals BREQO Bus mode signal Wait WAIT controller WCRH...
Page 160 7.1.3 Pin Configuration Table 7-1 summarizes the pins of the bus controller. Table 7-1 Bus Controller Pins Name Symbol Function Address strobe Output Strobe signal indicating that address output on address bus is enabled. Read Output Strobe signal indicating that external space is being read.
Page 161 Name Symbol Function WAIT Wait Input Wait request signal when accessing external 3-state access space. BREQ Bus request Input Request signal that releases bus to external device. BACK Bus request Output Acknowledge signal indicating that bus has been acknowledge released. BREQO Bus request output Output...
Page 162 Register Descriptions 7.2.1 Bus Width Control Register (ABWCR) ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value : Mode 4 Initial value : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access.
Page 163 7.2.2 Access State Control Register (ASTCR) AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
Page 164 7.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode.
Page 165 Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 5 is accessed...
Page 166 (2) WCRL Initial value Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Page 167 Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 1 is accessed...
Page 168 7.2.4 Bus Control Register H (BCRH) ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMTS0 Initial value BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode.
Page 169 Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access.
Page 170 7.2.5 Bus Control Register L (BCRL) BRLE BREQOE — RCTS WDBE WAITE Initial value — BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Page 171 Bit 3—DACK Timing Select (DDS): When using the DRAM interface, this bit selects the DMAC single address transfer bus timing. Bit 3 Description When performing DMAC single address transfers to DRAM, always execute full access. The DACK signal is output as a low-level signal from the T or T cycle.
Page 172 7.2.6 Pin Function Control Register (PFCR) CSS07 CSS36 BUZZE LCASS Initial value PFCR is an 8-bit read/write register that controls the CS selection of pins PG4 and PG1, controls LCAS selection of pins PF2 and PF6, and controls the address output in expanded mode with ROM.
Page 173 Bit 5—BUZZ Output Enable (BUZZE): This bit enables/disables BUZZ output via the PF1 pin. The WDT1 input clock, selected with PSS and CKS2 to CKS0, is output as the BUZZ signal. See Section 15.2.4, Pin Function Control Register (PFCR) for details of BUZZ output. Bit 5 BUZZE Description...
Page 174 Bit 3 Bit 2 Bit 1 Bit 0 Description A8–A23 address output disabled (Initial value*) A8 address output enabled; A9–A23 address output disabled A8, A9 address output enabled; A10–A23 address output disabled A8–A10 address output enabled; A11–A23 address output disabled A8–A11 address output enabled;...
Page 175 7.2.7 Memory Control Register (MCR) RCDM MXC1 MXC0 RLW1 RLW0 Initial value The MCR is an 8-bit read/write register that, when areas 2 to 5 are set as the DRAM interface, controls the DRAM strobe method, number of precharge cycles, access mode, address multiplex shift amount, and number of wait states to be inserted when a refresh is performed.
Page 176 Bit 4—Reserved (CW2): Only write 0 to this bit. Bits 3 and 2—Multiplex shift counts 1 and 0 (MXC1 and MXC0): These bits select the shift amount to the low side of the row address of the multiplexed row/column address in DRAM interface mode.
Page 177 7.2.8 DRAM Control Register (DRAMCR) RFSHE CBRM RMODE CMIE CKS2 CKS1 CKS0 Initial value The DRAMCR is an 8-bit read/write register that selects DRAM refresh mode, the refresh counter clock, and sets the refresh timer control. The DRAMCR is initialized to H'00 at a power-on reset and in hardware standby mode. It is not initialized at a manual reset or in software standby mode.
Page 178 Bit 4—Compare Match Flag (CMF): This status flag shows a match between RTCNT and RTCOR values. When performing refresh control (RFSHE=1), write 1 to CMF when writing to the DRAMCR. Bit 4 Description [Clearing] When CMF=1, read the CMF flag, then clear the CMF flag to 0. (Initial value) [Setting] CMF is set when RTCNT=RTCOR.
Page 179 7.2.9 Refresh Timer Counter (RTCNT) Initial value RTCNT is an 8-bit read/write up-counter. RTCNT counts up using the internal clock selected by the DRAMCR CKS2 to CKS0 bits. When RTCNT matches the value in RTCOR (compare match), the DRAMCR CMF flag is set to 1 and RTCNT is cleared to H'00.
Page 180 (CS0 to CS7) can be output for each area. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 7-2 shows an outline of the memory map. Note: * Not available in the H8S/2633 Series. H'000000...
Page 181 7.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
Page 182 7.3.3 Memory Interfaces The H8S/2633 Series memory interfaces comprise a basic bus interface that allows direct connection or ROM, SRAM, and so on, DRAM interface with direct DRAM connection and a burst ROM interface that allows direct connection of burst ROM. The memory interface can be selected independently for each area.
Page 183 7.3.4 Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (7.4, 7.5 and 7.7) should be referred to for further details.
Page 184 7.3.5 Chip Select Signals This LSI allows chip select signals (CS0 to CS7) to be output for each of areas 0 to 7. The level of these signals is set Low when accessing the external space of the respective area. Figure 7-3 shows example CSn (where n=0 to 7) signal output timing.
Page 185 Basic Bus Interface 7.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7-3). 7.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data...
Page 186 16-Bit Access Space: Figure 7-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions.
Page 187 7.4.3 Valid Strobes Table 7-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Page 188 7.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle ø...
Page 189 8-Bit 3-State Access Space: Figure 7-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle ø...
Page 190 16-Bit 2-State Access Space: Figures 7-8 to 7-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.
Page 191 Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Note: n = 0 to 7 Figure 7-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
Page 192 Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 7-10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)
Page 193 16-Bit 3-State Access Space: Figures 7-11 to 7-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
Page 194 Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Note: n = 0 to 7 Figure 7-12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
Page 195 Bus cycle ø Address bus D15 to D8 Read Valid D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 7-13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
Page 196 7.4.5 Wait Control When accessing external space, the H8S/2633 Series can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin.
Page 197 Figure 7-14 shows an example of wait state insertion timing. By program wait By WAIT pin ø WAIT Address bus Read Data bus Read data HWR, LWR Write Data bus Write data indicates the timing of WAIT pin sampling. Note: Figure 7-14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled.
Page 198 DRAM Interface 7.5.1 Overview This LSI allows area 2 to 5 external space to be set as DRAM space and DRAM interfacing to be performed. With the DRAM interface, DRAM can be directly connected to the LSI. BCRH RMTS2 to RMTS0 allow the setting up of 2, 4, or 8MB DRAM space. Burst operation is possible using high-speed page mode.
Page 199 7.5.3 Address Multiplexing In the case of DRAM space, the row address and column address are multiplexed. With address multiplexing, the MXC1 and MXC0 bits of the MCR select the amount of shift in the row address. Table 7-6 shows the relationship between MXC1 and MXC0 settings and the shift amount. Table 7-6 MXC1 and MXC0 Settings vs Address Multiplexing Address Pin...
Page 200 7.5.5 DRAM Interface Pins Table 7-7 shows the pins used for the DRAM interface, and their functions. Table 7-7 DRAM Interface Pin Configuration In DRAM Mode Name Direction Function Write enable Output Write enable when accessing DRAM space in 2 CAS mode. LCAS LCAS Lower column address...
Page 201 When RCTS is set to 1, the CAS signal timing differs when reading and writing, being asserted Ω cycle earlier when reading. ø A23 to A0 column CSn (RAS) RCTS= 0 CAS, LCAS RCTS= 1 HWR (WE) Read D15 toD0 CAS, LCAS HWR (WE) Write...
Page 202 7.5.7 Precharge State Control When accessing DRAM, it is essential to secure a time for RAS precharging. In this LSI, it is therefore necessary to insert 1 T state when accessing DRAM space. By setting the TPC bit of the MCR to 1, T can be changed from 1 state to 2 states.
Page 203 7.5.8 Wait Control There are two methods of inserting wait states in DRAM access: (1) insertion of program wait states, and (2) insertion of pin waits via WAIT pin. (1) Insertion of Program Wait States Setting the ASTCR bit of an area set for DRAM to 1 automatically inserts from 0 to 3 wait states, as set by WCRH and WCRL, between the T state and T state.
Page 204 (2) Insertion of Pin Waits When the WAITE bit of BCRH is set to 1, wait input via the WAIT pin is valid regardless of the ASTCR AST bit. In this state, a program wait is inserted when the DRAM space is accessed. If the WAIT pin level is Low at the fall in ø...
Page 205 7.5.9 Byte Access Control When 16-bit DRAMs are connected, the 2 CAS method can be used as the control signal required for byte access. Figure 7-19 shows the 2 CAS method control timing. Figure 7-20 shows an example of connecting DRAM in high-speed page mode.
Page 206 This LSI 2CAS 4Mbit DRAM 256KB × 16-bit configuration (address shift set to 9 bits) 9-bit column address CS (RAS) UCAS LCAS LCAS HWR (WE) (Row address input: A8 to A0) (Column address input: A8 to A0) D15 to D0 D15 to D0 Figure 7-20 High-speed Page Mode DRAM...
Page 207 This LSI 2CAS 16Mbit DRAM 1MB × 16-bit configuration (address shift set to 10 bits) 10-bit column address CS2 (RAS) UCAS LCAS LCAS HWR (WE) (Row address input: A9 to A0) (Column address input: A9 to A0) D15 to D0 D15 to D0 CS3 (OE) Figure 7-21 Example Connection of EDO Page Mode DRAM (OES=1)
Page 208 (1) Operation Timing for Burst Access (High-Speed Page Mode) Figure 7-22 shows the operation timing for burst access. When the DRAM space is successively accessed, the CAS signal and column address output cycle (2 state) are continued as long as the row address is the same in the preceding and succeeding access cycles.
Page 209 (2) RAS Down Mode and RAS Up Mode Even when burst operation is selected, DRAM access may not be continuous, but may be interrupted by accessing another area. In this case, burst operation can be continued by keeping the RAS signal level Low while the other area is accessed and then accessing the same row address in the DRAM space.
Page 210 • RAS up mode To select RAS up mode, clear the RCDM bit of the MCR to 0. If DRAM access is interrupted to access another area, the RAS signal level returns to High. Burst operation is only possible when the DRAM space is contiguous. Figure 7-24 shows example timing in RAS up mode. Note that the RAS signal level does not return to High in burst ROM space access.
Page 211 7.5.11 Refresh Control This LSI has a DRAM refresh control function. There are two refresh methods: (1) CAS-before- RAS (CBR) and (2), self refresh. (1) CAS-Before-RAS (CBR) Refresh To select CBR refresh, set the RFSHE bit of DRAMCR to 1 and clear the RMODE bit to 0. In CBR refresh, the input clock selected with the CKS2 to CKS0 bits of DRAMCR are used for the RTCNT count-up.
Page 212 ø RTCNT H'00 RTCOR Refresh request signal and CMF bit setting signal Figure 7-26 Compare Match Timing Read access of Write access of normal space normal space ø A23 to A0 HWR (WE) Refresh cycle Figure 7-27 Example CBR Refresh Timing (CBRM=0)
Page 213 Normal space access request ø A23 to A0 HWR (WE) Refresh cycle Figure 7-28 Example CBR Refresh Timing (CBRM=1)
Page 214 (2) Self-Refresh One of the DRAM standby modes is the self-refresh mode (battery backup mode), in which the DRAM generates its own refresh timing and refresh address. To select self-refresh, set the RFSHE bit and RMODE bits of the DRAMCR to 1. Next, execute a SLEEP instruction to make a transition to software standby mode.
Page 215 DMAC Single Address Mode and DRAM Interface When burst mode is set for the DRAM interface, the DDS bit selects the output timing for the DACK signal. It also selects whether or not to perform burst access when accessing the DRAM space in DMAC single address mode.
Page 216 7.6.2 DDS=0 When the DRAM space is accessed in DMAC single address mode, always perform full access (normal access). The DACK output level changes to Low afer the T state in the case of the DRAM interface. In other than DMAC signle address mode, burst access is possible when the DRAM space is accessed.
Page 217 Burst ROM Interface 7.7.1 Overview In this LSI, the area 0 external space can be set as burst ROM space and burst ROM interfacing performed. Burst ROM space interfacing allows 16-bit ROM capable of burst access to be accessed at high-speed. The BRSTRM bit of BCRH sets area 0 as burst ROM space.
Page 218 Full access Burst access ø Low address only changes Address bus Data bus Read data Read data Read data Figure 7-32 (a) Example Burst ROM Access Timing (AST0=BRSTS1=1)
Page 219 Full access Burst access ø Low address only changes Address bus Data bus Read data Read data Read data Figure 7-32 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0) 7.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface.
Page 220 Idle Cycle 7.8.1 Operation When the H8S/2633 Series accesses external space , it can insert a 1-state idle cycle (T ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on.
Page 221 (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7-34 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Page 222 (3) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 7-35. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.
Page 223 (4) Notes The setting of the ICIS0 and ICIS1 bits is invalid when accessing the DRAM space. For example, if the 2nd of successive reads of different areas is a DRAM access, only the T cycle is inserted, not the T cycle.
Page 224 DRAM space read External read DRAM space read EXTAL Address CAS, LCAS Data bus Idle cycle Figure 7-37 (b) Example Idle Cycle Operation in RAS Down Mode (ICIS0=1) 7.8.2 Pin States in Idle Cycle Table 7-8 shows pin states in an idle cycle. Table 7-8 Pin States in Idle Cycle Pins...
Page 225 Write Data Buffer Function The H8S/2633 Series has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transmission to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1.
Page 226 In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2633 Series. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state.
Page 227 7.10.3 Pin States in External Bus Released State Table 7-9 shows pin states in the external bus released state. Table 7-9 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance High impedance High impedance High impedance...
Page 228 7.10.4 Transition Timing Figure 7-39 shows the timing for transition to the bus-released state. CPU cycle External bus released state cycle ø High impedance Address bus Address High impedance Data bus High impedance High impedance High impedance High impedance HWR, LWR BREQ BACK BREQO*...
Page 229 DRAM space read access External bus released ø A23 to A0 BREQ BACK Figure 7-40 Example Bus Release Transition Timing After DRAM Access (Reading DRAM) 7.10.5 Notes The external bus release function is deactivated when MSTPCR is set to H'FFFFFF or H'EFFFFF and a transition is made to sleep mode.
Page 230 7.11.1 Overview The H8S/2633 Series has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU, DTC, and DMAC which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
Page 231 7.12 Resets and the Bus Controller In a power-on reset, the H8S/2633 Series, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. The bus controller registers and internal states are retained at a manual reset. The current external bus cycle is executed to completion.
Page 232 Section 8 DMA Controller Overview The H8S/2633 Series has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 8.1.1 Features The features of the DMAC are listed below. • Choice of short address mode or full address mode Short address mode ...
Page 233 • Module stop mode can be set  The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode 8.1.2 Block Diagram A block diagram of the DMAC is shown in figure 8-1. Internal address bus Internal interrupts TGI0A...
Page 234 8.1.3 Overview of Functions Tables 8-1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 8-1 (1) Overview of DMAC Functions (Short Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination •...
Page 235 Table 8-1 (2) Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination • • Normal mode Auto-request Auto-request  Transfer request retained internally  Transfers continue for the specified number of times (1 to 65536) ...
Page 236 8.1.4 Pin Configuration Table 8-2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode.
Page 237 8.1.5 Register Configuration Table 8-3 summarizes the DMAC registers. Table 8-3 DMAC Registers Initial Channel Name Abbreviation R/W Value Address* Bus Width Memory address register 0A MAR0A Undefined H'FEE0 16 bits I/O address register 0A IOAR0A Undefined H'FEE4 16 bits Transfer count register 0A ETCR0A Undefined H'FEE6...
Page 238 Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 8-4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0.
Page 239 8.2.1 Memory Address Registers (MAR) — — — — — — — — Initial value : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address.
Page 240 8.2.2 I/O Address Register (IOAR) IOAR Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address.
Page 241 (2) Repeat Mode Transfer Number Storage ETCRH Initial value : Transfer Counter ETCRL Initial value : *: Undefined In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH.
Page 242 Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 7 DTSZ Description Byte-size transfer (Initial value) Word-size transfer Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented.
Page 243 DMABCR Bit 4 DTDIR Description Transfer with MAR as source address and IOAR as destination address (Initial value) Transfer with IOAR as source address and MAR as destination address Transfer with MAR as source address and DACK pin as write strobe Transfer with DACK pin as read strobe and MAR as destination address Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source).
Page 244 Channel B Bit 3 Bit 2 Bit 1 Bit 0 DTF3 DTF2 DTF1 DTF0 Description — (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmit-data-empty interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmit-data-empty interrupt Activated by SCI channel 1 reception complete interrupt...
Page 245 8.2.5 DMA Band Control Register (DMABCR) DMABCRH : FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Initial value : DMABCRL : DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A Initial value : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
Page 246 Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. Bit 13 SAE1 Description Transfer in dual address mode (Initial value) Transfer in single address mode This bit is invalid in full address mode.
Page 247 Bit 11 DTA1B Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1A data transfer factor setting.
Page 248 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. The conditions for the DTE bit being cleared to 0 are as follows: •...
Page 249 Bit 4 DTE0A Description Data transfer disabled (Initial value) Data transfer enabled Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Page 250 Bit 0 DTIE0A Description Transfer end interrupt disabled (Initial value) Transfer end interrupt enabled Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 8-4. 8.3.1 Memory Address Register (MAR) —...
Page 251 8.3.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. (1) Normal Mode ETCRA Transfer Counter...
Page 252 ETCRB Block Transfer Counter ETCRB Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size.
Page 253 Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 15 DTSZ Description Byte-size transfer (Initial value) Word-size transfer Bit 14—Source Address Increment/Decrement (SAID) Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed.
Page 254 Bits 10 to 7—Reserved: Can be read or written to. Bit 6—Destination Address Increment/Decrement (DAID) Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 6 Bit 5 DAID...
Page 255 • Block Transfer Mode Bit 3 Bit 2 Bit 1 Bit 0 DTF3 DTF2 DTF1 DTF0 Description — (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmit-data-empty interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmit-data-empty interrupt...
Page 256 8.3.5 DMA Band Control Register (DMABCR) DMABCRH : FAE1 FAE0 — — DTA1 — DTA0 — Initial value : DMABCRL : DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A Initial value : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
Page 257 Bits 13 and 12—Reserved: Can be read or written to. Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer.
Page 258 Bits 10 and 8—Reserved: Can be read or written to. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel.
Page 259 Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU.
Page 260 Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt. Bit 3 DTIE1B Description Transfer break interrupt disabled (Initial value) Transfer break interrupt enabled Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt.
Page 261 Register Descriptions (3) 8.4.1 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that only specific bits of DMACR for the specific channel and also DMATCR and DMABCR can be changed to prevent inadvertent changes being made to registers other than those for the channel concerned.
Page 262 DMAWER : — — — — WE1B WE1A WE0B WE0A Initial value : — — — — DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in standby mode. Bits 7 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Page 263 Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR. Bit 0 WE0A Description Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled (Initial value) Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the...
Page 264 Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output. Bit 4 TEE0 Description TEND0 pin output disabled (Initial value) TEND0 pin output enabled The TEND pins are assigned only to channel B in short address mode. The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source.
Page 265 Operation 8.5.1 Transfer Modes Table 8-5 lists the DMAC modes. Table 8-5 DMAC Transfer Modes Transfer Mode Transfer Source Remarks • • Short Dual (1) Sequential mode TPU channel 0 to 5 Up to 4 channels can address address compare match/input operate independently (2) Idle mode mode...
Page 266 Operation in each mode is summarized below. (1) Sequential mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed.
Page 267 • External request In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits. (6) Block transfer mode In response to a single transfer request, a block transfer of the specified block size is carried out.
Page 268 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Page 269 Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. Figure 8-4 shows an example of the setting procedure for sequential mode.
Page 270 8.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR.
Page 271 Figure 8-5 illustrates operation in idle mode. Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 8-5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
Page 272 Figure 8-6 shows an example of the setting procedure for idle mode. [1] Set each bit in DMABCRH. Idle mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Page 273 8.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR.
Page 274 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Page 275 Figure 8-7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) · (2 · (N–1)) Where : L = Value set in MAR Address B N = Value set in ETCR...
Page 276 Figure 8-8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. Repeat mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Page 277 8.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK).
Page 278 Figure 8-9 illustrates operation in single address mode (when sequential mode is specified). DACK Address T Transfer 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) ·...
Page 279 Figure 8-10 shows an example of the setting procedure for single address mode (when sequential mode is specified). [1] Set each bit in DMABCRH. Single address • Clear the FAE bit to 0 to select short address mode setting mode. •...
Page 280 8.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA.
Page 281 Figure 8-11 illustrates operation in normal mode. Address T Transfer Address T Address B Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) · (2 · (N–1)) DAID DTSZ Address + DAIDE · (–1) · (2 · (N–1)) Where : = Value set in MARA = Value set in MARB...
Page 282 For setting details, see section 8.3.4, DMA Controller Register (DMACR). Figure 8-12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. Normal mode setting • Set the FAE bit to 1 to select full address mode.
Page 283 8.5.7 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times.
Page 284 Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB.
Page 285 Figure 8-14 illustrates operation in block transfer mode when MARA is designated as a block area. Address T Address T Block area 1st block Transfer Consecutive transfer Address B of M bytes or words is performed in response to one request 2nd block Nth block...
Page 286 ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
Page 287 Start (DTE = DTME = 1) Transfer request? Acquire bus Read address specified by MARA SAID DTSZ MARA=MARA+SAIDE·(–1) ·2 Write to address specified by MARB DAID DTSZ MARB=MARB+DAIDE·(–1) ·2 ETCRAL=ETCRAL–1 ETCRAL=H'00 Release bus ETCRAL=ETCRAH BLKDIR=0 DAID DTSZ MARB=MARB–DAIDE·(–1) ·2 ·ETCRAH SAID DTSZ MARA=MARA–SAIDE·(–1)
Page 288 For details, see section 8.3.4, DMA Control Register (DMACR). Figure 8-16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. Block transfer • Set the FAE bit to 1 to select full address mode setting mode.
Page 289 8.5.8 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 8-12. Table 8-12 DMAC Activation Sources Short Address Mode Full Address Mode Block...
Page 290 activation source for more than one channel, the interrupt request flag is cleared when the highest- priority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit.
Page 291 DACK strobe, without regard to the address. Figure 8-17 shows the data bus in single address mode. HWR, LWR External Address bus A23 to A0 memory (Read) H8S/2633 (Write) D15 to D0 (high impedance) External device DACK Figure 8-17 Data Bus in Single Address Mode...
Page 292 8.5.9 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 8-18. In this example, word- size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed.
Page 293 8.5.10 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 8-19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. read read read...
Page 294 Full Address Mode (Cycle Steal Mode): Figure 8-20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. read write read...
Page 295 Full Address Mode (Burst Mode): Figure 8-21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16- bit, 2-state access space to external 16-bit, 2-state access space. read write read...
Page 296 Full Address Mode (Block Transfer Mode): Figure 8-22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. read write read...
Page 297 DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 8-23 shows an example of DREQ pin falling edge activated normal mode transfer. read write release read write release Bus release...
Page 298 Figure 8-24 shows an example of DREQ pin falling edge activated block transfer mode transfer. 1 block transfer 1 block transfer Bus release read write read write dead release dead release ø DREQ Transfer Transfer Transfer Transfer Address bus source destination source destination...
Page 299 DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 8-25 shows an example of DREQ level activated normal mode transfer. release read write release read write release ø...
Page 300 Figure 8-26 shows an example of DREQ level activated block transfer mode transfer. 1 block transfer 1 block transfer Bus release read right dead release read right dead release ø DREQ Transfer Transfer Transfer Transfer Address bus source destination source destination DMA control Idle...
Page 301 8.5.11 DMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 8-27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read...
Page 302 Figure 8-28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read dead ø Address bus DACK TEND Last transfer...
Page 303 Single Address Mode (Write): Figure 8-29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA write dead ø...
Page 304 Figure 8-30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write dead ø Address bus DACK TEND Last transfer...
Page 305 DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 8-31 shows an example of DREQ pin falling edge activated single address mode transfer. Bus release DMA single Bus release DMA single Bus release...
Page 306 DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 8-32 shows an example of DREQ pin low level activated single address mode transfer. Bus release DMA single Bus release DMA single release...
Page 307 8.5.12 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
Page 308 read single read single read ø Internal address Internal read signal External address DACK Figure 8-34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation.
Page 309 If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 8-13.
Page 310 8.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC, and the DMAC There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle.
Page 311 8.5.15 NMI Interrupts and DMAC When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1.
Page 312 8.5.16 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again.
Page 313 8.5.17 Clearing Full Address Mode Figure 8-38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and the DTME bit in Clearing full DMABCRL to 0;...
Page 314 Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 8-14 shows the interrupt sources and their priority order. Table 8-14 Interrupt Source Priority Order Interrupt Source Interrupt Interrupt Name Short Address Mode Full Address Mode Priority Order DEND0A Interrupt due to end of...
Page 315 Usage Notes DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
Page 316 (b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 8-41. CPU longword read DMA transfer cycle MAR upper MAR lower word read word read DMA read DMA write ø...
Page 317 Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
Page 318 Figure 8-42 shows an example in which a low level is not output at the TEND pin. read write ø Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. Figure 8-42 Example in Which Low Level is Not Output at TEND Pin Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
Page 319 Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1. Also, if internal DMAC activation has already been initiated when operation is aborted, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if DTA is set to 1.
Page 320 Section 9 Data Transfer Controller (DTC) Overview The H8S/2633 Series includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 9.1.1 Features The features of the DTC are: • Transfer possible over any number of channels ...
Page 321 9.1.2 Block Diagram Figure 9-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.
Page 322 9.1.3 Register Configuration Table 9-1 summarizes the DTC registers. Table 9-1 DTC Registers Name Abbreviation Initial Value Address* DTC mode register A —* Undefined —* DTC mode register B —* Undefined —* DTC source address register —* Undefined —* DTC destination address register —* Undefined —*...
Page 323 Register Descriptions 9.2.1 DTC Mode Register A (MRA) Initial value Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined — — — — — — — — MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer.
Page 324 Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 Description Normal mode Repeat mode Block transfer mode — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Page 325 After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2633 Series, and should always be written with 0.
Page 326 9.2.3 DTC Source Address Register (SAR) Initial value Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address.
Page 327 9.2.6 DTC Transfer Count Register B (CRB) Initial value Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined —...
Page 328 For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 9.2.8 DTC Vector Register (DTVECR) SWDTE...
Page 329 9.2.9 Module Stop Control Register A (MSTPCRA) MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : MSTPCRA is a 8-bit readable/writable register that performs module stop mode control. When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 330 Operation 9.3.1 Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels.
Page 331 The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed.
Page 332 9.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.
Page 333 The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. Note: * Not available in the H8S/2633 Series. DTC vector Register information...
Page 334 Table 9-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE* Priority Write to DTVECR Software DTVECR H'0400+ — High (DTVECR [6:0] <<1) IRQ0 External pin H'0420 DTCEA7 IRQ1 H'0422 DTCEA6 IRQ2 H'0424...
Page 335 Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE* Priority TGI3A (GR3A compare match/ H'0460 DTCEC5 High input capture) channel 3 TGI3B (GR3B compare match/ H'0462 DTCEC4 input capture) TGI3C (GR3C compare match/ H'0464 DTCEC3 input capture) TGI3D (GR3D compare match/ H'0466 DTCEC2 input capture)
Page 336 Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE* Priority CMIA2 (compare match A2) 8-bit timer H'04B8 DTCEF5 High channel 2 CMIB2 (compare match B2) H'04BA DTCEF4 CMIA3 (compare match A3) 8-bit timer H'04C0 DTCEF3 channel 3 CMIB3 (compare match B3) H'04C2 DTCEF2 IICI0 (1-byte transmit/reception...
Page 337 9.3.4 Location of Register Information in Address Space Figure 9-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas.
Page 338 9.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 9-5 lists the register information in normal mode and figure 9-6 shows memory mapping in normal mode.
Page 339 9.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
Page 340 9.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.
Page 341 First block · SAR or DAR or · Block area · Transfer Nth block Figure 9-8 Memory Mapping in Block Transfer Mode...
Page 342 9.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9-9 shows the memory map for chain transfer.
Page 343 9.3.9 Operation Timing Figures 9-10 to 9-12 show an example of DTC operation timing. ø DTC activation request request Data transfer Vector read Address Read Write Transfer Transfer information read information write Figure 9-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ø...
Page 344 ø DTC activation request request Data transfer Data transfer Vector read Address Read Write Read Write Transfer Transfer Transfer Transfer information information information information read write read write Figure 9-12 DTC Operation Timing (Example of Chain Transfer) 9.3.10 Number of DTC Execution States Table 9-8 lists execution statuses for a single DTC data transfer, and table 9-9 shows the number of states required for each execution status.
Page 345 Table 9-9 Number of States Required for Each Execution Status Chip Chip On-Chip I/O Object to be Accessed Registers External Devices Bus width Access states Execution Vector read — — — 6+2m 2 status Register — — — — — —...
Page 346 9.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1.
Page 347 9.3.12 Examples of Use of the DTC (1) Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0).
Page 348 (2) Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half.
Page 349 (3) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).
Page 350 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
Page 351 10.1 Overview The H8S/2633 Series has 10 I/O ports (ports 1, 3, 7 and A to G), and two input-only port (ports 4 and 9). Table 10-1 summarizes the port functions. The pins of each port also have other functions.
Page 352 Table 10-1 Port Functions Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port 1 • 8-bit I/O P17/PO15/TIOCB2/ 8-bit I/O port also functioning as DMA 8-bit I/O port controller output pins (DACK0, DACK1), TPU port PWM3/TCLKD also function- I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, ing as DMA •...
Page 353 Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port 7 • 8-bit I/O P77/TxD3 8-bit I/O port also functioning as 8-bit timer I/O 8-bit I/O port port pins (TMRI01, TMCI01, TMRI23, TMCI23, also function- P76/RxD3 TMO0, TMO1, TMO2, TMO3), DMAC I/O pins ing as 8-bit P75/TMO3/SCK3 (DREQ0, TEND0, DREQ1, TEND1), bus...
Page 354 Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port B • 8-bit I/O PB7/A15/TIOCB5 8-bit I/O port also functioning as TPU I/O pins 8-bit I/O port port (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3, also PB6/A14/TIOCA5 TIOCC3, TIOCB3, TIIOCA3) and address functioning as •...
Page 355 Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port F • 8-bit I/O PF7 /ø When DDR = 0: input port When port DDR = 0 (after When DDR = 1 (after reset): ø output reset): input port When DDR = 1: ø...
Page 356 10.2 Port 1 10.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), DMAC output pins (DACK0, DACK1), 14-bit PWM output pins (PWM2, PWM3) external interrupt pins (IRQ0 and IRQ1), and address bus output pins (A23 to A20).
Page 357 10.2.2 Register Configuration Table 10-2 shows the port 1 register configuration. Table 10-2 Port 1 Registers Name Abbreviation Initial Value Address* Port 1 data direction register P1DDR H'00 H'FE30 Port 1 data register P1DR H'00 H'FF00 Port 1 register PORT1 Undefined H'FFB0 Note: * Lower 16 bits of the address.
Page 358 Port 1 Register (PORT1) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins P17 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR.
Page 359 10.2.3 Pin Functions Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), DMAC output pins (DACK0 and DACK1), external interrupt input pins (IRQ0 and IRQ1), 14-bit PWM output pins (PWM2 and PWM3), and address bus output pins (A23 to A20).
Page 360 Selection Method and Pin Functions P16/PO14/ The pin function is switched as shown below according to the combination of TIOCA2/PWM2/ the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 IRQ1 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), OEA bit in DACR3, bit NDER14 in NDERH, and bit P16DDR.
Page 361 Selection Method and Pin Functions P15/PO13/ The pin function is switched as shown below according to the combination of TIOCB1/TCLKC the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.
Page 362 Selection Method and Pin Functions P14/PO12/ The pin function is switched as shown below according to the combination of TIOCA1/IRQ0 the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR.
Page 363 Selection Method and Pin Functions P13/PO11/ The pin function is switched as shown below according to the combination of TIOCD0/TCLKB/ the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, bit NDER11 in NDERH, and bit P13DDR.
Page 364 Selection Method and Pin Functions P13/PO11/ TPU Channel TIOCD0/TCLKB/ 0 Setting A23 (cont) MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000 B'0001 to — B'xx00 Other than B'xx00 B'0011 B'0100 B'0101 to B'1xxx B'0111 CCLR2 to — — —...
Page 365 Selection Method and Pin Functions P12/PO10/ The pin function is switched as shown below according to the combination of TIOCC0/TCLKA/ the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bits AE3 to AE0 in PFCR, bit NDER10 in NDERH, and bit P12DDR.
Page 366 Selection Method and Pin Functions P12/PO10/ TPU Channel TIOCC0/TCLKA/ 0 Setting A22 (cont) MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOC3 to IOC0 B'0000 B'0001 to B'xx00 Other than B'xx00 B'0011 B'0100 B'0101 to B'1xxx B'0111 CCLR2 to — — —...
Page 367 Selection Method and Pin Functions P11/PO9/TIOCB0/ The pin function is switched as shown below according to the combination of DACK1/A21 the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, and bits IOB3 to IOB0 in TIOR0H), bits AE3 to AE0 in PFCR, bit NDER9 in NDERH, SAE1 bit in DMABCRH, and bit P11DDR.
Page 368 Selection Method and Pin Functions P11/PO9/TIOCB0/ TPU Channel DACK1/A21 (cont) 0 Setting MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000 B'0001 to — B'xx00 Other than B'xx00 B'0011 B'0100 B'0101 to B'1xxx B'0111 CCLR2 to — — — —...
Page 369 Selection Method and Pin Functions P10/PO8/TIOCA0/ The pin function is switched as shown below according to the combination of DACK0/A20 the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bits AE3 to AE0 in PFCR, bit NDER8 in NDERH, SAE0 bit in DMABCRH, and bit P10DDR.
Page 370 Selection Method and Pin Functions P10/PO8/TIOCA0/ TPU Channel DACK0/A20 (cont) 0 Setting MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0001 to B'xx00 Other than B'xx00 B'0011 B'0100 B'0101 to B'1xxx B'0111 CCLR2 to — — — —...
Page 371 10.3 Port 3 10.3.1 Overview Port 3 is an 8-bit I/O port. Port 3 is a multi-purpose port for SCI I/O pins (TxD0, RxD0, SCK0, IrTxD, IrRxD, TxD1, RxD1, SCK1, TxD4, RxD4, SCK4), external interrupt input pins (IRQ4, IRQ5) and IIC I/O pins (SCL0, SDA0, SCL1, SDA1). All of the port 3 pin functions have the same operating mode.
Page 372 Port 3 Data Direction Register (P3DDR) P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value : P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit. Read is disenabled. If a read is carried out, undefined values are read out. By setting P3DDR to 1, the corresponding port 3 pins become output, and be clearing to 0 they become input.
Page 373 Port 3 Register (PORT3) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by the state of pins P37 to P30. PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled. Always carry out writing off output data of port 3 pins (P37 to P30) to P3DR without fail.
Page 374 10.3.3 Pin Functions The port 3 pins double as SCI I/O input pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). The functions of port 3 pins are shown in Table 10-5. Table 10-5 Port 3 Pin Functions Selection Method and Pin Functions P37/TxD4 Switches as follows according to combinations of SCR TE bit of SCI4 and the P37DDR bit.
Page 375 Selection Method and Pin Functions P34/RxD1/ Switches as follows according to combinations of ICCR0 ICE bit of IIC0, SCR RE bit SDA0 of SCI1, and the P34DDR bit. The SDA0 output format becomes NMOS open drain output, enabling direct bus driving.
Page 376 Selection Method and Pin Functions P31/RxD0/ Switches as follows according to combinations of SCR RE bit of SCI0 and the IrRxD P31DDR bit. P31DDR — Pin function P31 input pin P31 output pin* RxD0/IrRxD input pin Note: * When P31ODR = 1, it becomes NMOS open drain output. P30/TxD0/ Switches as follows according to combinations of SCR TE bit of SCI0 and the IrTxD...
Page 377 10.4 Port 4 10.4.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0, DA1). Port 4 pin functions are the same in all operating modes.
Page 378 10.4.2 Register Configuration Table 10-6 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 10-6 Port 4 Registers Name Abbreviation Initial Value Address* Port 4 register PORT4 Undefined H'FFB3...
Page 379 10.5 Port 7 10.5.1 Overview Port 7 is an 8-bit I/O port. Port 7 is a multipurpose port for the 8-bit timer I/O pins (TMRI01, TMCI01, TMRI23, TMCI23, TMO0, TMO1, TMO2, TMO3), DMAC I/O pins (DREQ0, TEND0, DREQ1, TEND1), bus control output pins (CS4 to CS7), IIC input pin (SYNCI), SCI I/O pins (SCK3, RxD3, TxD3) and manual reset input pin (MRES).
Page 380 10.5.2 Register Configuration Table 10-7 shows the port 7 register configuration. Table 10-7 Port 7 Register Configuration Name Abbreviation Initial Value Address* Port 7 data direction register P7DDR H'00 H'FE36 Port 7 data register P7DR H'00 H'FF06 Port 7 register PORT7 Undefined H'FFB6...
Page 381 Port 7 Data Register (P7DR) P77DR P76DR P75DR P74DR P73DR P72DR P71DR P70DR Initial value : P7DR is an 8-bit readable/writable register, which stores the output data of port 7 pins (P77 to P70). P7DR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous state is maintained by a manual reset and in software standby mode.
Page 382 10.5.3 Pin Functions The pins of port 7 are multipurpose pins which function as 8-bit timer I/O pins, (TMRI01, TMCI01, TMRI23, TMCI23, TMO0, TMO1, TMO2, TMO3), DMAC I/O pins (DREQ0, TEND0, DREQ1, TEND1), bus control output pins (CS4 to CS7), IIC input pin (SYNCI), SCI I/O pins (SCK3, RxD3, TxD3) and manual reset input pin (MRES).
Page 383 Selection Method and Pin Functions P74/TMO2/ Switches as follows according to combinations of TCSR2 OS3 to OS0 bits of the 8- MRES bit timer, SYSCR MRESE bit and the P74DDR bit. MRESE OS3 to OS0 All 0 Any is 1 —...
Page 384 Selection Method and Pin Functions P71/TMRI23/ Switches as follows according to operating mode and P71DDR. TMCI23/ Operating Modes 4 to 6 Mode 7 DREQ1/CS5 Mode P71DDR CS5 output Pin function P71 input Pin P71 input pin P71 output pin DREQ0, DREQ0, TMRI23, TMCI23 input —...
Page 385 10.6 Port 9 10.6.1 Overview Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins (AN8 to AN15) and D/A converter analog output pins (DA2, DA3). Port 9 pin functions are the same in all operating modes.
Page 386 10.6.2 Register Configuration Table 10-9 shows the port 9 register configuration. Port 9 is an input-only port, and does not have a data direction register or data register. Table 10-9 Port 9 Registers Name Abbreviation Initial Value Address* Port 9 register PORT9 Undefined H'FFB8...
Page 387 10.7 Port A 10.7.1 Overview Port A is a 6-bit I/O port. Port A pins also function as address bus outputs and SCI2 I/O pins (SCK2, RxD2, and TxD2). The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software. Figure 10-6 shows the port A pin configuration.
Page 388 10.7.2 Register Configuration Table 10-10 shows the port A register configuration. Table 10-10 Port A Registers Name Abbreviation Initial Value* Address* Port A data direction register PADDR H'FE39 Port A data register PADR H'FF09 Port A register PORTA Undefined H'FFB9 Port A MOS pull-up control register PAPCR H'FE40...
Page 389 Port A Data Register (PADR) — — — — PA3DR PA2DR PA1DR PA0DR Initial value : Undefined Undefined Undefined Undefined — — — — PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to PA0).
Page 390 Port A MOS Pull-Up Control Register (PAPCR) — — — — PA3PCR PA2PCR PA1PCR PA0PCR Initial value : Undefined Undefined Undefined Undefined — — — — PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. Bits 7 to 4 are reserved;...
Page 391 10.7.3 Pin Functions Modes 4 to 6: In modes 4 to 6, port A pins function as address outputs according to the setting of AE3 to AE0 in PFCR; when they do not function as address outputs, the pins function as SCI I/O pins and I/O ports.
Page 392 In mode 7, if a pin is in the input state in accordance with the settings in the SCI’s SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode.
Page 393 10.8 Port B 10.8.1 Overview Port B is an 8-bit I/O port. Port B pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5) and as address outputs; the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software.
Page 394 10.8.2 Register Configuration Table 10-12 shows the port B register configuration. Table 10-12 Port B Registers Name Abbreviation Initial Value Address* Port B data direction register PBDDR H'00 H'FE3A Port B data register PBDR H'00 H'FF0A Port B register PORTB Undefined H'FFBA Port B MOS pull-up control register...
Page 395 Port B Data Register (PBDR) PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value : PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state by a manual reset or in software standby mode.
Page 396 Port B MOS Pull-Up Control Register (PBPCR) PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.
Page 397 10.8.3 Pin Functions Modes 4 to 6: In modes 4 to 6, the corresponding port B pins become address outputs in accordance with the setting of bits AE3 to AE0 in PFCR. When pins are not used as address outputs, they function as TPU I/O pins and I/O ports. Port B pin functions in modes 4 to 6 are shown in figure 10-10.
Page 398 10.8.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.
Page 399 10.9 Port C 10.9.1 Overview Port C is an 8-bit I/O port. Port C has a 14-bit PWM output (PWM0, PWM1) and an address bus output function. The pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 10-12 shows the port C pin configuration.
Page 400 10.9.2 Register Configuration Table 10-14 shows the port C register configuration. Table 10-14 Port C Registers Name Abbreviation Initial Value Address* Port C data direction register PCDDR H'00 H'FE3B Port C data register PCDR H'00 H'FF0B Port C register PORTC Undefined H'FFBB Port C MOS pull-up control register...
Page 401 Port C Data Register (PCDR) PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value : PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state by a manual reset or in software standby mode.
Page 402 Port C MOS Pull-Up Control Register (PCPCR) PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis. In modes 6 and 7, if PCPCR is set to 1 when the port is in the input state in accordance with the settings of DACR and PCDDR in PWM, the MOS input pull-up is set to ON.
Page 403 10.9.3 Pin Functions for Each Mode (1) Modes 4 and 5 In mode 4 and 5, port C pins function as address outputs automatically. Figure 10-13 shows the port C pin functions. (output) (output) (output) (output) Port C (output) (output) (output) (output) Figure 10-13 Port C Pin Functions (Modes 4 and 5)
Page 404 (3) Mode 7 In mode 7, port C pins function as PWM outputs and I/O ports and I/O can be specified for each pin in bit units. When each bit in PCDDR is set to 1, the corresponding pin functions as an output port and when the bit is cleared to 0, the pin functions as an input port.
Page 405 10.9.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis.
Page 406 10.10 Port D 10.10.1 Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 10-16 shows the port D pin configuration.
Page 407 10.10.2 Register Configuration Table 10-16 shows the port D register configuration. Table 10-16 Port D Registers Name Abbreviation Initial Value Address* Port D data direction register PDDDR H'00 H'FE3C Port D data register PDDR H'00 H'FF0C Port D register PORTD Undefined H'FFBC Port D MOS pull-up control register...
Page 408 Port D Data Register (PDDR) PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial value : PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state by a manual reset or in software standby mode.
Page 409 Port D MOS Pull-Up Control Register (PDPCR) PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis. When a PDDDR bit is cleared to 0 (input port setting) in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
Page 410 Port D pin functions in mode 7 are shown in figure 10-18. (I/O) (I/O) (I/O) (I/O) Port D (I/O) (I/O) (I/O) (I/O) Figure 10-18 Port D Pin Functions (Mode 7) 10.10.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis.
Page 411 10.11 Port E 10.11.1 Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 10-19 shows the port E pin configuration.
Page 412 10.11.2 Register Configuration Table 10-18 shows the port E register configuration. Table 10-18 Port E Registers Address * Name Abbreviation Initial Value Port E data direction register PEDDR H'00 H'FE3D Port E data register PEDR H'00 H'FF0D Port E register PORTE Undefined H'FFBD...
Page 413 Port E Data Register (PEDR) PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial value : PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state by a manual reset or in software standby mode.
Page 414 Port E MOS Pull-Up Control Register (PEPCR) PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis. When a PEDDR bit is cleared to 0 (input port setting) with 8-bit bus mode selected in mode 4, 5, or 6, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
Page 415 Mode 7: In mode 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.
Page 416 10.12 Port F 10.12.1 Overview Port F is an 8-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), BUZZ output pin, A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (ø) output pin.
Page 417 10.12.2 Register Configuration Table 10-20 shows the port F register configuration. Table 10-20 Port F Registers Address * Name Abbreviation Initial Value H'80/H'00 * Port F data direction register PFDDR H'FE3E Port F data register PFDR H'00 H'FF0E Port F register PORTF Undefined H'FFBE...
Page 418 Pins PF2 to PF0 are designated as bus control input/output pins (LCAS, WAIT, BREQO, BACK, BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port.
Page 419 10.12.3 Pin Functions Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), BUZZ output pin, A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (ø) output pin. The pin functions differ between modes 4 to 6, and mode 7.
Page 420 Selection Method and Pin Functions PF3/LWR/ADTRG/ The pin function is switched as shown below according to the operating mode, IRQ3 the bus mode, A/D converter bits TRGS1 and TRGS0, and bit PF3DDR. Operating Modes 4 to 6 Mode 7 mode Bus mode 16-bit bus 8-bit bus mode...
Page 421 Selection Method and Pin Functions PF0/BREQ/IRQ2 The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF0DDR. Operating Mode Modes 4 to 6 Mode 7 BRLE — PF0DDR — BREQ Pin function input pin output pin...
Page 422 10.13.2 Register Configuration Table 10-22 shows the port G register configuration. Table 10-22 Port G Registers Name Abbreviation Initial Value* Address* Port G data direction register PGDDR H'10/H'00* H'FE3F Port G data register PGDR H'00 H'FF0F Port G register PORTG Undefined H'FFBF Notes: 1.
Page 423 See Chapter 7 for the DRAM interface. • Mode 7 PGDDR to 1 it becomes an output port, and by clearing it to 0 it becomes an input port. Port G Data Register (PGDR) — — — PG4DR PG3DR PG2DR PG1DR PG0DR Initial value :...
Page 424 10.13.3 Pin Functions Port G is used also as external interrupt input pins (IRQ6, IRQ7) and bus control signal output pins (CS0 to CS3, CAS, OE). The pin functions are different between modes 4 and 6, and mode 7. Table 10-23 shows the port G pin functions. Table 10-23 Port G Pin Functions Selection Method and Pin Functions PG4/CS0...
Page 425 Selection Method and Pin Functions PG1/CS3/ The pin function is switched as shown below according to the operating mode and OE/IRQ7 bits OES and PG1DDR in BCRL. Operating Modes 4 to 6 Mode 7 Mode PG1DDR — — — Pin function input pin output pin output pin...
Page 426 Section 11 16-Bit Timer Pulse Unit (TPU) 11.1 Overview The H8S/2633 Series has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 11.1.1 Features • Maximum 16-pulse input/output  A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,...
Page 427 • 26 interrupt sources  For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently  For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently •...
Page 428 Table 11-1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 ø/1 ø/1 ø/1 ø/1 ø/1 Count clock ø/1 ø/4 ø/4 ø/4 ø/4 ø/4 ø/4 ø/16 ø/16 ø/16 ø/16 ø/16 ø/16 ø/64 ø/64 ø/64 ø/64 ø/64 ø/64...
Page 429 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DMAC TGR0A TGR1A TGR2A TGR3A TGR4A TGR5A activation compare compare compare compare compare compare match or match or match or match or match or match or input capture input capture input capture input capture...
Page 430 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the TPU. Interrupt request signals Channel 3: TGI3A Input/output pins TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4 TGI4B TIOCB4 TCI4V Channel 5: TIOCA5 TCI4U TIOCB5...
Page 431 11.1.3 Pin Configuration Table 11-2 summarizes the TPU pins. Table 11-2 TPU Pins Channel Name Symbol Function Clock input A TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) Clock input B TCLKB Input External clock B input pin...
Page 432 Channel Name Symbol Function Input capture/out TIOCA3 TGR3A input capture input/output compare compare match A3 output/PWM output pin Input capture/out TIOCB3 TGR3B input capture input/output compare compare match B3 output/PWM output pin Input capture/out TIOCC3 TGR3C input capture input/output compare compare match C3 output/PWM output pin Input capture/out...
Page 433 11.1.4 Register Configuration Table 11-3 summarizes the TPU registers. Table 11-3 TPU Registers Channel Name Abbreviation Initial Value Address * Timer control register 0 TCR0 H'00 H'FF10 Timer mode register 0 TMDR0 H'C0 H'FF11 Timer I/O control register 0H TIOR0H H'00 H'FF12 Timer I/O control register 0L...
Page 434 Channel Name Abbreviation Initial Value Address* Timer control register 3 TCR3 H'00 H'FE80 Timer mode register 3 TMDR3 H'C0 H'FE81 Timer I/O control register 3H TIOR3H H'00 H'FE82 Timer I/O control register 3L TIOR3L H'00 H'FE83 Timer interrupt enable register 3 TIER3 H'40 H'FE84 Timer status register 3...
Page 435 11.2 Register Descriptions 11.2.1 Timer Control Register (TCR) Channel 0: TCR0 Channel 3: TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2...
Page 436 Bits 7, 6, 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing source. Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture...
Page 437 Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
Page 438 Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 (Initial value) Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 439 Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 (Initial value) Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input Internal clock: counts on ø/1024 Internal clock: counts on ø/256 Internal clock: counts on ø/4096...
Page 440 11.2.2 Timer Mode Register (TMDR) Channel 0: TMDR0 Channel 3: TMDR3 — — Initial value : — — Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 — — — — Initial value : — — — —...
Page 441 Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved.
Page 442 11.2.3 Timer I/O Control Register (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : Channel 0: TIOR0L Channel 3: TIOR3L IOD3 IOD2 IOD1...
Page 443 Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR0B is Output disabled...
Page 444 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR0D is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register* Toggle output at compare match Output disabled Initial output is 1...
Page 445 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR1B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 446 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR3B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 447 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR3D is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register* Toggle output at compare match Output disabled Initial output is 1...
Page 448 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR4B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 449 Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR0A is Output disabled...
Page 450 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description TGR0C is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register* Toggle output at compare match Output disabled Initial output is 1...
Page 451 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR1A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 452 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR3A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 453 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description TGR3C is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register* Toggle output at compare match Output disabled Initial output is 1...
Page 454 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR4A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 455 11.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Channel 3: TIER3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : — — Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 TTGE — TCIEU TCIEV —...
Page 456 Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE Description A/D conversion start request generation disabled (Initial value) A/D conversion start request generation enabled Bit 6—Reserved: This bit is always read as 1 and cannot be modified. Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5.
Page 457 Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGIEC Description...
Page 458 11.2.5 Timer Status Register (TSR) Channel 0: TSR0 Channel 3: TSR3 — — — TCFV TGFD TGFC TGFB TGFA Initial value : — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, for flag clearing. Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4...
Page 459 Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD Description...
Page 460 Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD Description...
Page 461 Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB Description [Clearing conditions] (Initial value) • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 •...
Page 462 11.2.6 Timer Counter (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel.
Page 463 11.2.7 Timer General Register (TGR) Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers.
Page 464 11.2.8 Timer Start Register (TSTR) — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : — — TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Page 465 11.2.9 Timer Synchro Register (TSYR) — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value : — — TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Page 466 11.2.10 Module Stop Control Register A (MSTPCRA) MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA5 bit in MSTPCRA is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 467 11.3 Interface to Bus Master 11.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 11-2.
Page 468 Examples of 8-bit register access operation are shown in figures 11-3, 11-4, and 11-5. Internal data bus Module Bus interface master data bus Figure 11-3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus Module master Bus interface data bus...
Page 469 11.4 Operation 11.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting.
Page 470 11.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 11-6 shows an example of the count operation setting procedure.
Page 471 • Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
Page 472 Figure 11-8 illustrates periodic counter operation. Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DTC/DMAC activation Figure 11-8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
Page 473 • Examples of waveform output operation Figure 11-10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
Page 474 Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Page 475 • Example of input capture operation Figure 11-13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 476 11.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation.
Page 477 Example of Synchronous Operation: Figure 11-15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 478 11.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 11-5 shows the register combinations used in buffer operation.
Page 479 • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 11-17. Input capture signal Timer general...
Page 480 Examples of Buffer Operation • When TGR is an output compare register Figure 11-19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 481 • When TGR is an input capture register Figure 11-20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 482 11.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Page 483 Examples of Cascaded Operation: Figure 11-22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
Page 484 11.4.6 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register.
Page 485 Table 11-7 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGR0A TIOCA0 TIOCA0 TGR0B TIOCB0 TGR0C TIOCC0 TIOCC0 TGR0D TIOCD0 TGR1A TIOCA1 TIOCA1 TGR1B TIOCB1 TGR2A TIOCA2 TIOCA2 TGR2B TIOCB2 TGR3A TIOCA3 TIOCA3 TGR3B TIOCB3...
Page 486 Example of PWM Mode Setting Procedure: Figure 11-24 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 487 TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 11-25 Example of PWM Mode Operation (1) Figure 11-26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform.
Page 488 Figure 11-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...
Page 489 11.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 490 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 11-29 shows an example of phase counting mode 1 operation, and table 11-9 summarizes the TCNT up/down-count conditions.
Page 491 • Phase counting mode 2 Figure 11-30 shows an example of phase counting mode 2 operation, and table 11-10 summarizes the TCNT up/down-count conditions. TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCNT value Up-count Down-count...
Page 492 • Phase counting mode 3 Figure 11-31 shows an example of phase counting mode 3 operation, and table 11-11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 493 • Phase counting mode 4 Figure 11-32 shows an example of phase counting mode 4 operation, and table 11-12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 494 Phase Counting Mode Application Example: Figure 11-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Page 495 Channel 1 TCLKA Edge TCNT1 detection TCLKB circuit TGR1A (speed period capture) TGR1B (position period capture) TCNT0 TGR0A (speed control period) – TGR0C – (position control period) TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 11-33 Phase Counting Mode Application Example...
Page 496 11.5 Interrupts 11.5.1 Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Page 497 Table 11-13 TPU Interrupts Interrupt DMAC Channel Source Description Activation Activation Priority TGI0A TGR0A input capture/compare match Possible Possible High TGI0B TGR0B input capture/compare match Not possible Possible TGI0C TGR0C input capture/compare match Not possible Possible TGI0D TGR0D input capture/compare match Not possible Possible TCI0V TCNT0 overflow Not possible Not possible...
Page 498 Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
Page 499 11.6 Operation Timing 11.6.1 Input/Output Timing TCNT Count Timing: Figure 11-34 shows TCNT count timing in internal clock operation, and figure 11-35 shows TCNT count timing in external clock operation. ø Falling edge Rising edge Internal clock TCNT input clock TCNT N–1 Figure 11-34 Count Timing in Internal Clock Operation...
Page 500 Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin.
Page 501 Timing for Counter Clearing by Compare Match/Input Capture: Figure 11-38 shows the timing when counter clearing by compare match occurrence is specified, and figure 11-39 shows the timing when counter clearing by input capture occurrence is specified. ø Compare match signal Counter clear signal H'0000...
Page 502 Buffer Operation Timing: Figures 11-40 and 11-41 show the timing in buffer operation. ø TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 11-40 Buffer Operation Timing (Compare Match) ø Input capture signal TCNT TGRA, TGRB TGRC, TGRD Figure 11-41 Buffer Operation Timing (Input Capture)
Page 503 11.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 11-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. ø TCNT input clock TCNT Compare match signal...
Page 504 TGF Flag Setting Timing in Case of Input Capture: Figure 11-43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. ø Input capture signal TCNT TGF flag TGI interrupt Figure 11-43 TGI Interrupt Timing (Input Capture)
Page 505 TCFV Flag/TCFU Flag Setting Timing: Figure 11-44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 11-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
Page 506 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11-46 shows the timing for status flag clearing by the CPU, and figure 11-47 shows the timing for status flag clearing by the DTC or DMAC.
Page 507 11.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.
Page 508 Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 11-49 shows the timing in this case. TCNT write cycle ø...
Page 509 Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11-50 shows the timing in this case. TCNT write cycle ø...
Page 510 Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 11-51 shows the timing in this case.
Page 511 Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 11-52 shows the timing in this case. TGR write cycle ø...
Page 512 Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11-53 shows the timing in this case. TGR read cycle ø...
Page 513 Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11-54 shows the timing in this case. TGR write cycle ø...
Page 514 Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11-55 shows the timing in this case. Buffer register write cycle ø...
Page 515 Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11-56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Page 516 Figure 11-57 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the H8S/2633 Series, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.
Page 517 12.1 Overview The H8S/2633 Series has a built-in programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 and group 2) that can operate both simultaneously and independently.
Page 518 12.1.2 Block Diagram Figure 12-1 shows a block diagram of the PPG. Compare match signals NDERH NDERL Control logic PO15 Pulse output PO14 PO13 pins, group 3 PO12 Internal PODRH NDRH PO11 data bus Pulse output PO10 pins, group 2 Pulse output pins, group 1 PODRL...
Page 519 12.1.3 Pin Configuration Table 12-1 summarizes the PPG pins. Table 12-1 PPG Pins Name Symbol Function Pulse output 8 Output Group 2 pulse output Pulse output 9 Output Pulse output 10 PO10 Output Pulse output 11 PO11 Output Pulse output 12 PO12 Output Group 3 pulse output...
Page 520 PCR setting, the NDRL address is H'FE2D. When the output triggers are different, the NDRL address is H'FE2F for group 0 and H'FE2D for group 1. 4. The H8S/2633 Series has no pins corresponding to pulse output groups 0 and 1.
Page 521 12.2 Register Descriptions 12.2.1 Next Data Enable Registers H and L (NDERH, NDERL) NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value : NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis.
Page 522 Note: * A bit that has been set for pulse output by NDER is read-only. PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output. However, the H8S/2633 Series has no pins corresponding to PODRL.
Page 523 H'FE2D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FE2F consists entirely of reserved bits that cannot be modified and are always read as 1. However, the H8S/2633 Series has no output pins corresponding to pulse output groups 0 and 1.
Page 524 H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that cannot be modified and are always read as 1. However, the H8S/2633 Series has no output pins corresponding to pulse output groups 0 and 1.
Page 525 Address H'FE2D NDR7 NDR6 NDR5 NDR4 — — — — Initial value : — — — — Address H'FE2F — — — — NDR3 NDR2 NDR1 NDR0 Initial value : — — — — 12.2.5 PPG Output Control Register (PCR) G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a...
Page 526 Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match that triggers pulse output group 1 (pins PO7 to PO4). However, the H8S/2633 Series has no output pins corresponding to pulse output group 1. Bit 3...
Page 527 12.2.6 PPG Output Mode Register (PMR) G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value : PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB and the non-overlap margin is set in TGRA.
Page 528 Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). However, the H8S/2633 Series has no pins corresponding to pulse output group 1. Bit 5 G1INV Description Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)
Page 529 Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4). However, the H8S/2633 Series has no pins corresponding to pulse output group 1. Bit 1 G1NOV Description Normal operation in pulse output group 1 (output values updated at compare match A...
Page 530 12.2.7 Port 1 Data Direction Register (P1DDR) P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1.
Page 531 12.3 Operation 12.3.1 Overview PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
Page 532 12.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. ø...
Page 533 12.3.3 Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 12-4 shows a sample procedure for setting up normal pulse output. [1] Set TIOR to make TGRA an output Normal PPG output compare register (with output disabled) Select TGR functions [2] Set the PPG output trigger period Set TGRA value [3] Select the counter clock source...
Page 534 Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 12-5 shows an example in which pulse output is used for cyclic five-phase pulse output. Compare match TCNT value TCNT TGRA H'0000 Time NDRH PODRH PO15 PO14 PO13 PO12 PO11 Figure 12-5 Normal Pulse Output Example (Five-Phase Pulse Output) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output...
Page 535 12.3.4 Non-Overlapping Pulse Output Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 12-6 shows a sample procedure for setting up non-overlapping pulse output. [1] Set TIOR to make TGRA and Non-overlapping PPG output TGRB an output compare registers (with output disabled) Select TGR functions [2] Set the pulse output trigger period in TGRB and the non-overlap...
Page 536 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 12-7 shows an example in which pulse output is used for four- phase complementary non-overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 Time NDRH PODRH Non-overlap margin PO15 PO14 PO13...
Page 537 [1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt.
Page 538 12.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12-7.
Page 539 12.3.6 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal.
Page 540 12.4 Usage Notes Operation of Pulse Output Pins: Pins PO8 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins.
Page 541 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC.
Page 542 13.1 Overview The H8S/2633 Series includes an 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events.
Page 543 13.1.2 Block Diagram Figure 13-1 shows a block diagram of the 8-bit timer module (TMR0, TMR1). External clock source Internal clock sources TMCI01 ø/8 ø/64 TMCI23 ø/8192 Clock 1 Clock select Clock 0 TCORA0 TCORA1 Compare match A1 Comparator A0 Comparator A1 Compare match A0 Overflow 1...
Page 544 13.1.3 Pin Configuration Table 13-1 summarizes the input and output pins of the 8-bit timer. Table 13-1 Pin Configuration Channel Name Symbol Function Timer output pin 0 TMO0 Output Outputs at compare match Timer clock input pin 01 TMCI01 Input Inputs external clock for counter Timer reset input pin 01 TMRI01 Input...
Page 545 13.1.4 Register Configuration Table 13-2 summarizes the registers of the 8-bit timer module. Table 13-2 8-Bit Timer Registers Channel Name Abbreviation Initial value Address* Timer control register 0 TCR0 H'00 H'FF68 Timer control/status register 0 TCSR0 R/(W)* H'00 H'FF6A Time constant register A0 TCORA0 H'FF H'FF6C...
Page 546 13.2 Register Descriptions 13.2.1 Timer Counters 0 to 3 (TCNT0 to TCNT3) TCNT0 (TCNT2) TCNT1 (TCNT3) Initial value TCNT0 to TCNT3 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. This clock source is selected by clock select bits CKS2 to CKS0 of TCR.
Page 547 The timer output can be freely controlled by these compare match signals and the settings of bits OS1 and OS0 of TCSR. TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode. 13.2.3 Time Constant Registers B0 to B3 (TCORB0 to TCORB3) TCORB0 (TCORB2) TCORB1 (TCORB3) Initial value...
Page 548 Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag of TCSR is set to 1. Bit 7 CMIEB Description CMFB interrupt requests (CMIB) are disabled (Initial value) CMFB interrupt requests (CMIB) are enabled Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag of TCSR is set to 1.
Page 549 Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (ø): ø/8, ø/64, and ø/8192. The falling edge of the selected internal clock triggers the count.
Page 550 13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3) TCSR0 CMFB CMFA ADTE Initial value R/(W)* R/(W)* R/(W)* TCSR1, TCSR3 CMFB CMFA — Initial value R/(W)* R/(W)* R/(W)* — TCSR2 CMFB CMFA — Initial value R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Page 551 Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match. Bit 7 CMFB Description [Clearing conditions] (Initial value) • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 [Setting condition] Set when TCNT matches TCORB...
Page 552 Bit 4—A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare-match A. TCSR1 to TCSR3 are reserved bits. When TCSR1 and TCSR3 are read, always 1 is read off. Write is disenabled. TCSR2 is readable/writable. Bit 4 ADTE Description...
Page 553 13.2.6 Module Stop Control Register A (MSTPCRA) MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA4 and MSTPA0 bits in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 554 13.3 Operation 13.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (ø/8, ø/64, or ø/8192) divided from the system clock (ø) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 13-2 shows the count timing.
Page 555 ø External clock input Clock input to TCNT TCNT N–1 Figure 13-3 Count Timing for External Clock Input 13.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated.
Page 556 Timer Output Timing: When compare match A or B occurs, the timer output changes a specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 13-5 shows the timing when the output is set to toggle at compare match A.
Page 557 13.3.3 Timing of External RESET on TCNT TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 13-7 shows the timing of this operation.
Page 558 13.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit timer channel 0 could be counted by the timer of channel 1 (compare match counter mode).
Page 559 13.4 Interrupts 13.4.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in Table 13-3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller.
Page 560 13.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 13-9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA.
Page 561 13.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer. 13.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed.
Page 562 13.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 13-11 shows this operation. TCNT write cycle by CPU ø...
Page 563 13.6.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is disabled even if a compare match event occurs. Figure 13-12 shows this operation. TCOR write cycle by CPU ø...
Page 564 13.6.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13-4.
Page 565 Table 13-5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from Clock before low to low* switchover Clock after switchover TCNT clock TCNT CKS bit write Switching from Clock before low to high* switchover...
Page 566 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock before Switching from high switchover to high Clock after switchover TCNT clock TCNT CKS bit write Notes: 1. Includes switching from low to stop, and from stop to low. 2.
Page 567 Section 14 14-Bit PWM D/A 14.1 Overview The H8S/2633 Series has an on-chip 14-bit pulse-width modulator (PWM) with four output channels. Each channel can be connected to an external low-pass filter to operate as a 14-bit D/A converter. Both channels share the same counter (DACNT) and control register (DACR).
Page 568 14.1.2 Block Diagram Figure 14-1 shows a block diagram of the PWM D/A module. Internal clock Internal data bus ø ø/2 Clock Bus interface Clock selection Basic cycle compare-match A Fine-adjustment Comparator PWM0 DADRA pulse addition A Basic cycle PWM1 compare-match B Comparator DADRB...
Page 569 14.1.3 Pin Configuration Table 14-1 lists the pins used by the PWM D/A module. Table 14-1 Input and Output Pins Name Abbr. Function PWM output pin 0 PWM0 Output PWM output, channel 0A PWM output pin 1 PWM1 Output PWM output, channel 0B PWM output pin 2 PWM2 Output...
Page 570 14.2 Register Descriptions 14.2.1 PWM D/A Counter (DACNT) DACNTH DACNTL Bit (CPU) — — BIT (Counter) REGS Initial value — DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse. The input clock is selected by the clock select bit (CKS) in DACR. The CPU can read and write the DACNT value, but since DACNT is a 16-bit register, data transfers between it and the CPU are performed using a temporary register (TEMP).
Page 571 14.2.2 PWM D/A Data Registers A and B (DADRA and DADRB) DADRH DADRL Bit (CPU) — — Bit (Data) DA13 DA12 DA11 DA10 — DADRA Initial value : — DADRB DA13 DA12 DA11 DA10 REGS Initial value : There are two 16-bit readable/writable PWM D/A data registers: DADRA and DADRB. DADRA corresponds to PWM D/A channel A, and DADRB to PWM D/A channel B.
Page 572 Bit 1—Carrier Frequency Select (CFS) Bit 1 Description Base cycle = resolution (T) × 64 DADR range = H'0401 to H'FFFD Base cycle = resolution (T) × 256 (Initial value) DADR range = H'0103 to H'FFFF Bit 0—Reserved: This bit cannot be modified and is always read as 1. DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are located at the same addresses.
Page 573 Bit 7—Test Mode (TEST): Selects test mode, which is used in testing the chip. Normally this bit should be cleared to 0. Bit 7 TEST Description PWM (D/A) in user state: normal operation (Initial value) PWM (D/A) in test state: correct conversion results unobtainable Bit 6—PWM Enable (PWME): Starts or stops the PWM D/A counter (DACNT).
Page 574 Bit 0—Clock Select (CKS): Selects the PWM D/A resolution. If the system clock (ø) frequency is 10 MHz, resolutions of 100 ns and 200 ns can be selected. Bit 0 Description Operates at resolution (T) = system clock cycle time (t (Initial value) ) ×...
Page 575 14.3 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written and read as follows (taking the example of the CPU interface).
Page 576 Upper-Byte Write Module data bus interface (H'AA) Upper byte TEMP (H'AA) DACNTH DACNTL Lower-Byte Write Module data bus interface (H'57) Lower byte TEMP (H'AA) DACNTH DACNTL (H'AA) (H'57) Figure 14-2 (a) Access to DACNT (CPU Writes H'AA57 to DACNT)
Page 577 Upper-Byte Read Module data bus interface (H'AA) Upper byte TEMP (H'57) DACNTH DACNTL (H'AA) (H'57) Lower-Byte Read Module data bus interface (H'57) Lower byte TEMP (H'57) DACNTH DACNTL Figure 14-2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT)
Page 578 14.4 Operation A PWM waveform like the one shown in figure 14-3 is output from the PWMX pin. When OS = 0, the value in DADR corresponds to the total width (T ) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1).
Page 579 Table 14-4 Settings and Operation (Examples when ø = 10 MHz) Fixed DADR Bits Bit Data Resolution Base Conversion (if OS = 0) Precision Conversion T (µs) Cycle (µs) Cycle (µs) (if OS = 1) (Bits) 3 2 1 0 Cycle* (µs) 1638.4 1638.4...
Page 580 1. OS = 0 (DADR corresponds to T a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle f255 f256 L255 L256 = T × 64 = · · · = t f255 f256 + · · · + t L255 L256 Figure 14-4 (1) Output Waveform...
Page 581 2. OS = 1 (DADR corresponds to T a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle f255 f256 H255 H256 = T × 64 = · · · = t f255 f256 + · · · + t H255 H256 Figure 14-4 (3) Output Waveform...
Page 582 15.1 Overview The H8S/2633 Series has a two channel inbuilt watchdog timer, (WDT0/WDT1). The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the H8S/2633 Series.
Page 583 15.1.2 Block Diagram Figure 15-1 (a) and 15-1 (b) show a block diagram of the WDT. Overflow ø/2 Interrupt ø/64 WOVI 0 control ø/128 (interrupt request ø/512 signal) Clock Clock select ø/2048 ø/8192 ø/32768 WDTOVF Reset ø/131072 control Internal reset signal * Internal clock sources RSTCSR...
Page 584 ø/2 øSUB/2 ø/64 WOVI1 øSUB/4 ø/128 Interrupt (Interrupt request signal) øSUB/8 ø/512 control Clock Overflow øSUB/16 Clock Internal NMI select ø/2048 øSUB/32 Interrupt request signal ø/8192 Reset øSUB/64 ø/32768 control øSUB/128 ø/131072 Internal reset signal* øSUB/256 Internal clock BUZZ TCNT TCSR interface Module bus...
Page 585 15.1.3 Pin Configuration Table 15-1 describes the WDT output pin. Table 15-1 WDT Pin Name Symbol Function WDTOVF Watchdog timer overflow Output Outputs counter overflow signal in watchdog timer mode Buzzer output BUZZ Output Outputs clock selected by watchdog timer (WDT1) 15.1.4 Register Configuration...
Page 586 15.2 Register Descriptions 15.2.1 Timer Counter (TCNT) Initial value : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF) or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.
Page 587 TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 588 WDT1 Mode Select WDT1 WT/IT Description Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows. (Initial value) Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows. Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Page 589 WDT0 TCSR Bit 3—Reserved Bit: This bit is always read as 1 and cannot be modified. WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal reset request and an NMI request when the TCNT overflows during the watchdog timer mode. Bit 3 RTS/NMI Description...
Page 590 WDT1 Input Clock Select Description Bit 4 Bit 2 Bit 1 Bit 0 Overflow Period* (where ø = 25 MHz) CKS2 CKS1 CKS0 Clock (where ø SUB = 32.768 kHz) ø/2 (initial value) 20.4 µs ø/64 652.8 µs ø/128 1.3 ms ø/512 5.2 ms ø/2048...
Page 591 Bit 6 RSTE Description Reset signal is not generated if TCNT overflows* (Initial value) Reset signal is generated if TCNT overflows Note: * The modules within the H8S/2633 Series are not reset, but TCNT and TCSR within the WDT are reset.
Page 592 Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. For details of the types of reset, see section 4, Exception Handling. Bit 5 RSTS Description Power-on reset (Initial value) Manual reset Bits 4 to 0—Reserved: These bits are always read as 1 and cannot be modified.
Page 593 15.2.5 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions.
Page 594 Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address H'FF76. It cannot be written to with byte instructions. Figure 15-3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits.
Page 595 130 states when RSTE = 0. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2633 Series internally is generated at the same time as the WDTOVF signal. This reset can be selected as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR.
Page 596 TCNT count Overflow H'FF Time H'00 WOVF=1 WT/IT=1 H'00 written WT/IT=1 H'00 written WDTOVF and TME=1 to TCNT TME=1 to TCNT internal reset are generated WDTOVF signal 132 states * Internal reset signal * 518 states Legend : Timer mode select bit WT/IT : Timer enable bit Notes: 1.
Page 597 15.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 15-5.
Page 598 WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2633 Series chip. Figure 15-7 shows the timing in this case.
Page 599 15.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated when a TCNT overflow occurs.
Page 600 15.5.5 Internal Reset in Watchdog Timer Mode The H8S/2633 Series is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCSR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period.
Page 601 Section 16 Serial Communication Interface (SCI, IrDA) 16.1 Overview The H8S/2633 is equipped with 5 independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).
Page 602  Receive error detection : Overrun errors detected • Full-duplex communication capability  The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously  Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data •...
Page 603 16.1.2 Block Diagram Figure 16-1 shows a block diagram of the SCI. Internal Module data bus data bus SCMR ø ø/4 Baud rate generator ø/16 Transmission/ ø/64 reception control Parity generation Clock Parity check External clock Legend : Receive shift register : Receive data register : Transmit shift register : Transmit data register...
Page 604 16.1.3 Pin Configuration Table 16-1 shows the serial pins for each SCI channel. Table 16-1 SCI Pins Channel Pin Name Symbol* Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0/IrRxD Input SCI0 receive data input (normal/IrDA) Transmit data pin 0 TxD0/IrTxD Output SCI0 transmit data output (normal/IrDA)
Page 605 16.1.4 Register Configuration The SCI has the internal registers shown in table 16-2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. Table 16-2 SCI Registers Channel Name Abbreviation...
Page 606 Channel Name Abbreviation Initial Value Address* Serial mode register 3 SMR3 H'00 H'FDD0 Bit rate register 3 BRR3 H'FF H'FDD1 Serial control register 3 SCR3 H'00 H'FDD2 Transmit data register 3 TDR3 H'FF H'FDD3 Serial status register 3 SSR3 R/(W)* H'84 H'FDD4 Receive data register 3...
Page 607 16.2 Register Descriptions 16.2.1 Receive Shift Register (RSR) — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data.
Page 608 16.2.3 Transmit Shift Register (TSR) — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically.
Page 609 16.2.5 Serial Mode Register (SMR) STOP CKS1 CKS0 Initial value SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode.
Page 610 Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting.
Page 611 Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description...
Page 612 Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.8, Bit Rate Register.
Page 613 Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request...
Page 614 Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description...
Page 615 Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin.
Page 616 16.2.7 Serial Status Register (SSR) TDRE RDRF ORER TEND MPBT Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits.
Page 617 Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF Description [Clearing conditions] (Initial value) • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is...
Page 618 Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 Description [Clearing condition] (Initial value)* • When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * Notes: 1.
Page 619 Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND Description [Clearing conditions] •...
Page 620 16.2.8 Bit Rate Register (BRR) Initial value BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in standby mode.
Page 621 Table 16-3 BRR Settings for Various Bit Rates (Asynchronous Mode) ø = 2 MHz ø = 2.097152 MHz ø = 2.4576 MHz ø = 3 MHz Bit Rate Error Error Error Error (bit/s) 0.03 –0.04 1 –0.26 1 0.03 0.16 0.21 0.00 0.16...
Page 622 ø = 6 MHz ø = 6.144 MHz ø = 7.3728 MHz ø = 8 MHz Bit Rate Error Error Error Error (bit/s) –0.44 2 0.08 –0.07 2 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 1200 0.16...
Page 623 ø = 14 MHz ø = 14.7456 MHz ø = 16 MHz ø = 17.2032 MHz Bit Rate Error Error Error Error (bit/s) –0.17 3 0.70 0.03 0.48 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 1200 0.16 0.00...
Page 624 Table 16-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ø = 2 MHz ø = 4 MHz ø = 8 MHz ø = 10 MHz ø = 16 MHz ø = 20 MHz ø = 25 MHz Bit Rate (bit/s) —...
Page 625 The BRR setting is found from the following formulas. Asynchronous mode: ø × 10 – 1 64 × 2 × B 2n–1 Clocked synchronous mode: ø × 10 – 1 8 × 2 × B 2n–1 Where B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤...
Page 626 Table 16-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 16-6 and 16-7 show the maximum bit rates with external clock input. Table 16-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ø (MHz) Maximum Bit Rate (bit/s) 62500 2.097152 65536...
Page 627 Table 16-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Page 628 Table 16-7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 3.3333 3333333.3 4.1667...
Page 629 16.2.9 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value — — — — — SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication mode.
Page 630 Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in SMR. Bit 2 SINV Description TDR contents are transmitted without modification (Initial value)
Page 631 Bits 6 to 4—IrDA clock select 2 to 0 (IrCKS2 to IrCKS0): When the IrDA function is enabled, these bits set the width of the High pulse when encoding the IrTxD output pulse. Bit 6 Bit 5 Bit 4 IrCKS2 IrCKS1 IrCKS0 Description...
Page 632 MSTPCRB and MSTPCRC are initialized to H'FF by a reset and in hardware standby mode. They are not initialized by a manual reset and in software standby mode. (1) Module Stop Control Register B (MSTPCRB) Bit 7—Module Stop (MSTPB7): Specifies the SCI0 module stop mode. Bit 7 MSTPB7 Description...
Page 633 Bit 6—Module Stop (MSTPC6): Specifies the SCI4 module stop mode. Bit 6 MSTPC6 Description SCI4 module stop mode is cleared SCI4 module stop mode is set (Initial value) 16.3 Operation 16.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses.
Page 634  When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip  When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock Table 16-8 SMR Settings and Serial Transfer Format Selection SMR Settings SCI Transfer Format...
Page 635 Table 16-9 SMR and SCR Settings and SCI Clock Source Selection SCR Setting SCI Transmit/Receive Clock Bit 7 Bit 1 Bit 0 Clock CKE1 CKE0 Mode Source SCK Pin Function Asynchronous Internal SCI does not use SCK pin mode Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times...
Page 636 16.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication.
Page 637 Data Transfer Format: Table 16-10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 16-10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP...
Page 638 Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 16-9.
Page 639 Figure 16-4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Start initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCR to 0 When the clock is selected in asynchronous mode, it is output Set CKE1 and CKE0 bits in SCR...
Page 640 • Serial data transmission (asynchronous mode) Figure 16-5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin.
Page 641 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Page 642 Figure 16-6 shows an example of the operation for transmission in asynchronous mode. Start Data Parity Stop Start Data Parity Stop Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt TEI interrupt request generated TDRE flag cleared to 0 in request generated request generated...
Page 643 • Serial data reception (asynchronous mode) Figure 16-7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start reception input pin.
Page 644 Error processing ORER= 1 Overrun error processing FER= 1 Break? Framing error processing Clear RE bit in SCR to 0 PER= 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 16-7 Sample Serial Reception Data Flowchart (cont)
Page 645 In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received.
Page 646 Table 16-11 Receive Errors and Conditions for Occurrence Receive Error Abbreviation Occurrence Condition Data Transfer Overrun error ORER When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 RDR.
Page 647 16.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines.
Page 648 Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID= 01) (ID= 02) (ID= 03) (ID= 04) Serial H'01 H'AA data (MPB= 1) (MPB= 0) ID transmission cycle= Data transmission cycle= receiving station Data transmission to specification receiving station specified by ID...
Page 649 SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and Read TDRE flag in SSR transmission is enabled. SCI status check and transmit TDRE= 1 data write:...
Page 650 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Page 651 Figure 16-11 shows an example of SCI operation for transmission using the multiprocessor format. Multi- Multi- proce- Start Data Stop Start Data Stop ssor proces- sor bit Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request generated and TDRE flag cleared to...
Page 652 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start reception input pin. ID reception cycle: Read MPIE bit in SCR Set the MPIE bit in SCR to 1. Read ORER and FER flags in SSR SCI status check, ID reception and comparison: Read SSR and check that the...
Page 653 Error processing ORER= 1 Overrun error processing FER= 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 16-12 Sample Multiprocessor Serial Reception Flowchart (cont)
Page 654 Figure 16-13 shows an example of SCI operation for multiprocessor format reception. Start Data (ID1) Stop Start Data (Data1) Stop Idle state (mark state) MPIE RDRF value MPIE = 0 RXI interrupt RDR data read If not this station’s ID, RXI interrupt request is request and RDRF flag...
Page 655 16.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer.
Page 656 Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external clock as the clock source.
Page 657 • Serial data transmission (clocked synchronous mode) Figure 16-16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start transmission pin.
Page 658 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Page 659 • Serial data reception (clocked synchronous mode) Figure 16-18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible.
Page 660 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start reception input pin. [2] [3] Receive error processing: Read ORER flag in SSR If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag ORER= 1...
Page 661 In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR.
Page 662 SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the Start transmission/reception receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR SCI status check and transmit data write: Read SSR and check that the TDRE= 1...
Page 663 16.3.5 IrDA Operation Figure 16-21 is a block diagram of the IrDA. When the IrE bit of IrCR is set to enable the IrDA function, the TxD0/RxD0 signals of SCI channel 0 are encoded and decoded with waveforms conforming to the IrDA standard version 1.0 (IrTxD/IrRxD pins).
Page 664 When the value of the serial data is “1”, no pulse is output. UART frame Data Start Start Transmitting Receiving IR frame Data Start Start Pulse width = 1.6 µs to cycle 3/16ths bit cycle Figure 16-22 IrDA Transmit and Receive Operations (2) Receiving When receiving, the IR frame data is converted into UART frames by the IrDA interface and input to the SCI.
Page 665 Table 16-12 Setting Bits IrCKS2 to IrCKS0 Bit Rate (bps) (Upper Row) / Bit Cycle × 3/16 (µs) (Lower Row) 2400 9600 19200 38400 57600 115200 Operating Frequency (MHz) 78.13 19.53 9.77 4.88 3.26 1.63 — 2.097152 — 2.4576 — —...
Page 666 16.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 16-13 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently.
Page 667 Table 16-13 SCI Interrupt Sources Interrupt DMAC Channel Source Description Activation Activation Priority* Interrupt due to receive error (ORER, FER, Not possible Not possible High or PER) Interrupt due to receive data full state Possible Possible (RDRF) Interrupt due to transmit data empty state Possible Possible (TDRE)
Page 668 A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance, with the result that the TDRE and TEND flags are cleared.
Page 669 Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set.
Page 670 16 clocks 8 clocks 15 0 15 0 Internal basic clock Receive data Start bit (RxD) Synchronization sampling timing Data sampling timing Figure 16-23 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. | D –...
Page 671 Restrictions on Use of DMAC or DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ø clock cycles after TDR is updated by the DMAC or DTC. Misoperation may occur if the transmit clock is input within 4 ø...
Page 672 • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid.
Page 673 Transition Exit from End of to software software Start of transmission transmission standby standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Start Stop Port input/output High output SCI TxD Port Port SCI TxD output output Figure 16-26 Asynchronous Transmission Using Internal Clock Transition...
Page 674 <Reception> Read RDRF flag in SSR Receive data being received be- RDRF= 1 comes invalid. Read receive data in RDR RE= 0 Transition to software [2] Includes module stop mode, watch standby mode, etc. mode, subactive mode, and sub- sleep mode. Exit from software standby mode, etc.
Page 675 Switching from SCK Pin Function to Port Pin Function: • Problem in Operation: When switching the SCK pin function to the output port function (high- level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
Page 676 • Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown.
Page 677 Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 17.1.1 Features Features of the Smart Card interface supported by the H8S/2633 Series are as follows. • Asynchronous mode  Data length: 8 bits  Parity bit generation and checking ...
Page 678 17.1.2 Block Diagram Figure 17-1 shows a block diagram of the Smart Card interface. Internal Module data bus data bus SCMR ø ø/4 Baud rate generator ø/16 Transmission/ ø/64 reception control Parity generation Clock Parity check Legend : Smart Card mode register SCMR : Receive shift register : Receive data register...
Page 679 17.1.3 Pin Configuration Table 17-1 shows the Smart Card interface pin configuration. Table 17-1 Smart Card Interface Pins Channel Pin Name Symbol Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output...
Page 680 17.1.4 Register Configuration Table 17-2 shows the registers used by the Smart Card interface. Details of BRR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 16, Serial Communication Interface. Table 17-2 Smart Card Interface Registers Channel Name...
Page 681 Channel Name Abbreviation Initial Value Address* Serial mode register 3 SMR3 H'00 H'FDD0 Bit rate register 3 BRR3 H'FF H'FDD1 Serial control register 3 SCR3 H'00 H'FDD2 Transmit data register 3 TDR3 H'FF H'FDD3 Serial status register 3 SSR3 R/(W)* H'84 H'FDD4 Receive data register 3...
Page 682 17.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 17.2.1 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value : — — — —...
Page 683 Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 17.3.4, Register Settings.
Page 684 17.2.2 Serial Status Register (SSR) TDRE RDRF ORER TEND MPBT Initial value : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different.
Page 685 Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 16.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND Description Transmission is in progress [Clearing conditions] (Initial value) •...
Page 686 17.2.3 Serial Mode Register (SMR) BCP1 BCP0 CKS1 CKS0 Initial value : Note: When the smart card interface is used, be sure to make the 1 setting shown for bit 5. The function of bits 7, 6, 3, and 2 of SMR changes in Smart Card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode.
Page 687 Bit 6—Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 Description Normal Smart Card interface mode operation • Error signal transmission/detection and automatic data retransmission performed • TXI interrupt generated by TEND flag • TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) Block transfer mode operation •...
Page 688 17.2.4 Serial Control Register (SCR) MPIE TEIE CKE1 CKE0 Initial value : In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI.
Page 689 17.3 Operation 17.3.1 Overview The main functions of the Smart Card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame.
Page 690 Data line Clock line Rx (port) Reset line H8S/2633 Series IC card Connected equipment Figure 17-2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed...
Page 691 17.3.3 Data Format (1) Normal Transfer Mode Figure 17-3 shows the normal Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested.
Page 692 The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
Page 693 17.3.4 Register Settings Table 17-3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 17-3 Smart Card Interface Register Settings Register Bit 7 Bit 6...
Page 694 The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2633 Series, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies...
Page 695 17.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1 and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 17-5 shows some sample bit rates.
Page 696 The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified.
Page 697 17.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0.
Page 698 Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17-4 shows a flowchart for transmitting, and figure 17-5 shows the relation between a transmit operation and the internal registers.
Page 699 Start Initialization Start transmission ERS=0? Error processing TEND=1? Write data to TDR, and clear TDRE flag in SSR to 0 All data transmitted? ERS=0? Error processing TEND=1? Clear TE bit to 0 Figure 17-4 Example of Transmission Processing Flow...
Page 700 (shift register) (1) Data write Data 1 (2) Transfer from Data 1 Data 1 ; Data remains in TDR TDR to TSR Data 1 I/O signal line output (3) Serial data output Data 1 In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set...
Page 701 Serial Data Reception (Except Block Transfer Mode): Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 17-7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0.
Page 702 With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated.
Page 703 requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated.
Page 704 DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DMAC or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Note: For block transfer mode, see section 16.4, SCI Interrupts.
Page 705 Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation.
Page 706 17.4 Usage Notes The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (as determined by bits BCP1 and BCP0).
Page 707 Thus the reception margin in asynchronous mode is given by the following formula. Formula for reception margin in smart card interface mode  D – 0.5 (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, and 256) D: Clock duty (D = 0 to 1.0)
Page 708 Transfer nth transfer frame Retransferred frame frame n+1 (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 RDRF Figure 17-11 Retransfer Operation in SCI Receive Mode •...
Page 709 C bus interface is available as an option in the H8S/2633 Series. The I C bus interface is not available for the H8S/2633 Series. Observe the following notes when using this option. 1. For mask-ROM versions, a W is added to the part number in products in which this optional function is used.
Page 710 • Wait function in slave mode (I C bus format) A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. • Three interrupt sources ...
Page 711 ø ICCR Clock control Noise canceler ICMR Bus state decision circuit ICSR Arbitration decision circuit ICDRT Output data control ICDRS circuit ICDRR Noise canceler Address comparator SAR, SARX Interrupt Interrupt request generator Legend: ICCR: C bus control register ICMR: C bus mode register ICSR: C bus status register ICDR:...
Page 712 (Master) H8S/2633 Series chip (Slave 1) (Slave 2) Figure 18-2 I C Bus Interface Connections (Example: H8S/2633 Series Chip as Master) 18.1.3 Input/Output Pins Table 18-1 summarizes the input/output pins used by the I C bus interface. Table 18-1 I...
Page 713 18.1.4 Register Configuration Table 18-2 summarizes the registers of the I C bus interface. Table 18-2 Register Configuration Channel Name Abbreviation Initial Value Address* C bus control register ICCR0 H'01 H'FF78* C bus status register ICSR0 H'00 H'FF79* C bus data register ICDR0 —...
Page 714 18.2 Register Descriptions 18.2.1 C Bus Data Register (ICDR) ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 Initial value : — — — — — — — — • ICDRR ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 Initial value : —...
Page 715 ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only.
Page 716 TDRE Description The next transmit data is in ICDR (ICDRT), or transmission cannot (Initial value) be started [Clearing conditions] • When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) • When a stop condition is detected in the bus line state after a stop condition is issued with the I C bus format or serial format selected •...
Page 717 18.2.2 Slave Address Register (SAR) SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 Initial value : SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device.
Page 718 DDCSWR SARX Bit 6 Bit 0 Bit 0 Operating Mode C bus format • SAR and SARX slave addresses recognized C bus format (Initial value) • SAR slave address recognized • SARX slave address ignored C bus format • SAR slave address ignored •...
Page 719 Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in DDCSWR to select the communication format. • I C bus format: addressing format with acknowledge bit • Synchronous serial format: non-addressing format without acknowledge bit, for master mode only The FSX bit also specifies whether or not SARX slave address recognition is performed in slave mode.
Page 720 Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level).
Page 721 Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel 1) or IICX0 (channel 0) bit in the SCRX register, select the serial clock frequency in master mode. They should be set according to the required transfer rate. SCRX 5 or 6 Bit 5 Bit 4...
Page 722 Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit.
Page 723 Bit 7—I C Bus Interface Enable (ICE): Selects whether or not the I C bus interface is to be used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer operations are enabled. When ICE is cleared to 0, the I C bus interface module is halted and its internal states are cleared.
Page 724 Bit 5 Bit 4 Operating Mode Slave receive mode (Initial value) Slave transmit mode Master receive mode Master transmit mode Bit 5 Description Slave mode (Initial value) [Clearing conditions] 1. When 0 is written by software 2. When bus arbitration is lost after transmission is started in I C bus format master mode Master mode...
Page 725 ACKB bit, which is always 0. In the H8S/2633 Series, the DTC can be used to perform continuous transfer. The DTC is activated when the IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the other being IRIC).
Page 726 Bit 2 BBSY Description Bus is free (Initial value) [Clearing condition] When a stop condition is detected Bus is busy [Setting condition] When a start condition is detected Bit 1—I C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I C bus interface has issued an interrupt request to the CPU.
Page 727 Bit 1 IRIC Description Waiting for transfer, or transfer in progress (Initial value) [Clearing conditions] 1. When 0 is written in IRIC after reading IRIC = 1 2. When ICDR is written or read by the DTC (When the TDRE or RDRF flag is cleared to 0) (This is not always a clearing condition;...
Page 728 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set.
Page 729 Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1.
Page 730 Bit 7 ESTP Description No error stop condition (Initial value) [Clearing conditions] 1. When 0 is written in ESTP after reading ESTP = 1 2. When the IRIC flag is cleared to 0 • In I C bus format slave mode Error stop condition detected [Setting condition] When a stop condition is detected during frame transfer...
Page 731 Bit 5 IRTR Description Waiting for transfer, or transfer in progress (Initial value) [Clearing conditions] 1. When 0 is written in IRTR after reading IRTR = 1 2. When the IRIC flag is cleared to 0 Continuous transfer state [Setting condition] •...
Page 732 AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 3 Description Bus arbitration won...
Page 733 Bit 1—General Call Address Recognition Flag (ADZ): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode.
Page 734 18.2.7 Serial Control Register X (SCRX) — IICX1 IICX0 IICE FLSHE — — — Initial value : SCRX is an 8-bit readable/writable register that controls register access, the I C interface operating mode (when the on-chip IIC option is included), and on-chip flash memory control (F- ZTAT versions).
Page 735 18.2.8 DDC Switch Register (DDCSWR) — — — — CLR3 CLR2 CLR1 CLR0 Initial value : R/(W)* R/(W)* R/(W)* R/(W)* Notes: 1. Should always be written with 0. Always read as 1. DDCSWR is an 8-bit readable/writable register that is used to initialize the IIC module. DDCSWR is initialized to H'0F by a reset and in hardware standby mode.
Page 736 18.2.9 Module Stop Control Register B (MSTPCRB) MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : MSTPCRB is an 8-bit readable/writable register that perform module stop mode control. When the MSTPB4 or MSTPB3 bit is set to 1, operation of the corresponding IIC channel is halted at the end of the bus cycle, and a transition is made to module stop mode.
Page 737 18.3 Operation 18.3.1 C Bus Data Format The I C bus interface has serial and I C bus formats. The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures 18-3 (a) and (b). The first frame following a start condition always consists of 8 bits. The serial format is a non-addressing format with no acknowledge bit.
Page 738 DATA DATA Figure 18-5 I C Bus Timing Table 18-4 I C Bus Data Format Symbols Legend Start condition. The master device drives SDA from high to low while SCL is high Slave address, by which the master device selects a slave device Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge.
Page 739 ICDR using the timing shown in figure 18-6. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. (4) When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse.
Page 740 To transmit data continuously: (6) Before the rise of the 9th transmit clock pulse for the data being transmitted, clear the IRIC flag to 0 and then write the next transmit data to ICDR. (7) When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse.
Page 741 (2) When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. In order to determine the end of reception, the IRIC flag in ICCR must be cleared beforehand. (3) The master device drives SDA at the 9th receive clock pulse to return an acknowledge signal.
Page 742 Master transmit mode Master receive mode (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (slave output) Data 1 Data 2 (master output) RDRF Interrupt request Interrupt request IRIC generation generation...
Page 743 has been set to 1, the slave device drives SCL low from the fall of the receive clock until data is read into ICDR. (5) Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Receive operations can be performed continuously by repeating steps (4) and (5).
Page 744 (master output) (slave output) Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (master output) Data 1 Data 2 (slave output) RDRF Interrupt Interrupt IRIC request request generation generation ICDRS Data 1 Data 2...
Page 745 slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at the timing shown in figure 18-11. (4) When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse.
Page 746 18.3.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred;...
Page 747 18.3.7 Operation Using the DTC The I C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts.
Page 748 18.3.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 18-13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Page 749 Start Initialize [1] Test the status of the SCL and SDA lines. Read BBSY in ICCR [2] Select master transmit mode. [3] Generate a start condition. BBSY = 0? [4] Set transmit data for the first byte (slave address + R/W). [5] Wait for 1 byte to be transmitted.
Page 750 Master receive mode [1] Select receive mode. Set TRS = 0 in ICCR [2] Set acknowledge data. Set ACKB = 0 in ICSR [3] Start receiving. The first read is a dummy read. [4] Wait for 1 byte to be received. [5] Set acknowledge data for the last receive.
Page 751 Start Initialize Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Read IRIC in ICCR IRIC = 1? Read AAS and ADZ in ICSR AAS = 1 General call address processing and ADZ = 0? * Description omitted Read TRS in ICCR TRS = 0?
Page 752 Slave transmit mode [1] Set transmit data for the second and Clear IRIC in ICCR subsequent bytes. [2] Wait for 1 byte to be transmitted. Write transmit data in ICDR [3] Test for end of transfer. Clear IRIC in ICCR [4] Select slave receive mode.
Page 753 Scope of Initialization: The initialization executed by this function covers the following items: • TDRE and RDRF internal flags • Transmit/receive sequencer and internal operating clock counter • Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) The following items are not initialized: •...
Page 754 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or according to the ICE bit. 4. Initialize (re-set) the IIC registers. 18.4 Usage Notes • In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly.
Page 755 • SCL and SDA input is sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle t , as shown in table 25-11 in section 25, Electrical Characteristics. Note that the I C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz.
Page 756 investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the I bus.
Page 757 Table 18-8 I C Bus Timing (with Maximum Influence of t Time Indication (at Maximum Transfer Rate) [ns] C Bus Specifi- Influence cation ø = ø = ø = ø = ø = ø = Item Indication (Max.) (Min.) 5 MHz 8 MHz 10 MHz 16 MHz...
Page 758 Time Indication (at Maximum Transfer Rate) [ns] C Bus Specifi- Influence cation ø = ø = ø = ø = ø = ø = Item Indication (Max.) (Min.) 5 MHz 8 MHz 10 MHz 16 MHz 20 MHz 25 MHz Standard SDAHO mode...
Page 759 Stop condition Start condition Bit 0 Internal clock BBSY bit Master receive mode ICDR reading prohibited Execution of stop Confirmation of stop Start condition condition issuance condition generation issuance instruction (0 read from BBSY) (0 written to BBSY and SCP) Figure 18-18 Points for Attention Concerning Reading of Master Receive Data •...
Page 760 [1] Wait for end of 1-byte transfer IRIC= 1 ? [2] Determine whether SCL is low [3] Issue restart condition instruction for retransmission Clear IRIC in ICSR [4] Determine whether SCL is high Start condition Other processing issuance? [5] Set transmit data (slave address + R/W) Note: Program so that processing from [3] to [5] is Read SCL pin executed continuously.
Page 761 • Notes on I 2 C Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, issue the stop condition instruction after reading SCL and determining it to be low, as shown below.
Page 762 Section 19 A/D Converter 19.1 Overview The H8S/2633 Series incorporates a successive approximation type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. 19.1.1 Features A/D converter features are listed below. • 10-bit resolution • Sixteen input channels •...
Page 763 19.1.2 Block Diagram Figure 19-1 shows a block diagram of the A/D converter. Module data bus Internal data bus AVCC Vref 10-bit D/A AVSS ø/2 – ø/4 Comparator Control circuit ø/8 Sample-and- AN10 ø/16 hold circuit AN11 AN12 AN13 AN14 AN15 interrupt ADTRG...
Page 764 19.1.3 Pin Configuration Table 19-1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The 16 analog input pins are divided into two channel sets and two groups, with analog input pins 0 to 7 (AN0 to AN7) comprising channel set 0, analog input pins 8 to 15 (AN8 to AN15) comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (AN0 to AN3, AN8 to AN11)
Page 765 19.1.4 Register Configuration Table 19-2 summarizes the registers of the A/D converter. Table 19-2 A/D Converter Registers Name Abbreviation Initial Value Address* A/D data register AH ADDRAH H'00 H'FF90 A/D data register AL ADDRAL H'00 H'FF91 A/D data register BH ADDRBH H'00 H'FF92...
Page 766 19.2 Register Descriptions 19.2.1 A/D Data Registers A to D (ADDRA to ADDRD) — — — — — — Initial value There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there.
Page 767 19.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value R/(W)* Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Page 768 Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description...
Page 769 Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). Channel Selection Description Single Mode Scan Mode (SCAN = 0) (SCAN = 1)
Page 770 19.2.3 A/D Control Register (ADCR) TRGS1 TRGS0 — — CKS1 CKS0 — — Initial value — — — — ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations and sets the A/D conversion time. ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode.
Page 771 19.2.4 Module Stop Control Register A (MSTPCRA) MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value MSTPCR is a 8-bit readable/writable register that performs module stop mode control. When the MSTPA1 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 772 19.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP).
Page 773 19.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 19.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input.
Page 774 Set* ADIE Set* Set* conversion starts ADST Clear* Clear* State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle Idle Idle A/D conversion A/D conversion State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle ADDRA Read conversion result Read conversion result ADDRB...
Page 775 19.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0).
Page 776 Continuous A/D conversion execution Clear* Set* ADST Clear* A/D conversion time State of channel 0 (AN0) Idle Idle Idle A/D conversion 1 A/D conversion 4 State of channel 1 (AN1) Idle Idle Idle A/D conversion 2 A/D conversion 5 State of channel 2 (AN2) Idle Idle A/D conversion 3...
Page 777 19.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 19-5 shows the A/D conversion timing.
Page 778 Table 19-4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion start delay t —...
Page 779 19.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC and DMAC can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software.
Page 780 Also, digital circuitry must be isolated from the analog input signals (AN0 to AN15), analog reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board.
Page 781 To A/D converter 20 pF Note: Values are reference values. Figure 19-8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: H8S/2633 Series A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes •...
Page 782 Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 19-9 A/D Conversion Precision Definitions (1)
Page 783 Figure 19-10 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8S/2633 Series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 784 GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8S/2633 Series A/D converter equivalent circuit Sensor output impedance 10 kΩ...
Page 785 Section 20 D/A Converter 20.1 Overview The H8S/2633 Series has an on-chip D/A converter module with four channels. 20.1.1 Features Features of the D/A converter module are listed below. • Eight-bit resolution • Four-channel output • Maximum conversion time: 10 µs (with 20-pF load capacitance) •...
Page 786 Module data bus Internal data bus Vref AVCC DA1 (DA3) 8-bit D/A DA0 (DA2) AVSS Control circuit Legend: DACR: D/A control register DADR0 to DADR3: D/A data register 0 to 3 Figure 20-1 Block Diagram of D/A Converter...
Page 787 20.1.3 Input and Output Pins Table 20-1 lists the input and output pins used by the D/A converter module. Table 20-1 Input and Output Pins of D/A Converter Module Name Abbreviation Function Analog supply voltage AVCC Input Power supply for analog circuits Analog ground AVSS Input...
Page 788 20.2 Register Descriptions 20.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3) Initial value D/A data registers 0 to 3 (DADR0 to DADR3) are 8-bit readable/writable registers that store data to be converted. When analog output is enabled, the value in the D/A data register is converted and output continuously at the analog output pin.
Page 789 Enabled on channels 0 and 1 (channels 2 and 3) *: Don’t care If the H8S/2633 Series chip enters software standby mode while D/A conversion is enabled, the D/A output is retained and the analog power supply current is the same as during D/A conversion.
Page 790 20.2.3 Module Stop Control Register A and C (MSTPCRA and MSTPCRC) MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value MSTPCRA and MSTPCRC are an 8-bit readable/writable registers that performs module stop mode control.
Page 791 Module Stop Control Register A (MSTPCRA) Bit 2—Module Stop (MSTPA2): Specifies D/A converter (channels 0 and 1) module stop mode. Bit 2 MSTPA2 Description D/A converter (channels 0 and 1) module stop mode is cleared D/A converter (channels 0 and 1) module stop mode is set (Initial value) Module Stop Control Register C (MSTPCRC) Bit 5—Module Stop (MSTPC5): Specifies D/A converter (channels 2 and 3) module stop mode.
Page 792 20.3 Operation The D/A converter module has two built-in D/A converter circuits that can operate independently. D/A conversion is performed continuously whenever enabled by the D/A control register (DACR). When a new value is written in DADR0 or DADR1, conversion of the new value begins immediately.
Page 793 21.1 Overview The H8S/2633 has 16 kbytes of on-chip high-speed static RAM, the H8S/2632 has 12 kbytes, and the H8S/2631 has 8 kbytes. The RAM is connected to the CPU by a 16-bit data bus, enabling one- state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer.
Page 794 21.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 21-1 shows the address and initial value of SYSCR. Table 21-1 RAM Register Name Abbreviation Initial Value Address* System control register SYSCR H'01 H'FDE5 Note: * Lower 16 bits of the address. 21.2 Register Descriptions 21.2.1...
Page 795 When the RAME bit is set to 1, accesses to addresses H'FFB000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2633, to addresses H'FFC000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2632, and to addresses H'FFD000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2631, are directed to the on-chip RAM.
Page 796 Section 22 ROM 22.1 Features The H8S/2633 Series has 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode •...
Page 797 22.2 Overview 22.2.1 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating FWE pin Bus interface/controller mode Mode pin EBR1 EBR2 RAMER FLPWCR Flash memory (256 kbytes) Legend FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2:...
Page 798 22.2.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 22-2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory.
Page 799 The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the H8S/2633 (originally incorporated in the chip) programming control program and new is started and the programming control program application program beforehand in the host.
Page 800 Host Host Programming/ erase control program New application New application program program H8S/2633 H8S/2633 Boot program Boot program Flash memory Flash memory FWE assessment FWE assessment program program...
Page 801 22.2.4 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. Flash memory Emulation block Overlap RAM...
Page 802 Flash memory Programming data Overlap RAM Application program (programming data) Programming control program execution state Figure 22-4 Writing Overlap RAM Data in User Program Mode 22.2.5 Differences between Boot Mode and User Program Mode Table 22-1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase...
Page 803 22.2.6 Block Configuration The flash memory is divided into three 64 kbytes blocks, one 32 kbytes block, and eight 4 kbytes blocks. Address H'00000 × 4 kbytes 32 kbytes 256 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'3FFFF Figure 22-5 Flash Memory Block Configuration 22.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 22-2.
Page 804 22.4 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 22-3. In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER, SCRX). Table 22-3 Register Configuration Address * Register Name Abbreviation...
Page 805 Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled when FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 when FWE = 1, SWE1 = 1, and PSU1 = 1. Bit: SWE1 ESU1...
Page 806 Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode. Set this bit to 1 before setting the P1 bit in FLMCR1 to 1. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at the same time. Bit 4 PSU1 Description...
Page 807 Bit 1 Description Erase mode cleared (Initial value) Transition to erase mode [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 Bit 0—Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time.
Page 808 Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error- protection state. Bit 7 FLER Description Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition]...
Page 809 22.5.4 Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is not set, even though a high level is input to pin FWE.
Page 810 22.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. RAMER settings should be made in user mode or user program mode.
Page 811 Bits 2 to 0—Flash Memory Area Selection: These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 22-5.) Table 22-5 Flash Memory Area Divisions Addresses Block Name RAMS RAM1 RAM1 RAM0 H'FFD000–H'FFDFFF...
Page 812 22.5.6 Flash Memory Power Control Register (FLPWCR) Bit: PDWND — — — — — — — Initial value: R/W: FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode.
Page 813 The SCI channel to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2633 Series’ pins have been set to boot mode, the boot program built into the H8S/2633 Series is started and the programming control program prepared in the host is serially transmitted to the H8S/2633 Series via the SCI.
Page 814 The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 22-6, and the boot mode execution procedure in figure 22-7. H8S/2633 Series Flash memory Host Write data reception...
Page 815 H'00 data transmitted by host bytes (N), upper byte followed by lower byte H8S/2633 calculates bit rate and sets value in bit rate register H8S/2633 transmits received number of bytes to host as verify After bit rate adjustment, H8S/2633...
Page 816 Depending on the host’s transmission bit rate and the H8S/2633 Series’ system clock frequency, there will be a discrepancy between the bit rates of the host and the H8S/2633 Series. Set the host transfer bit rate at 2,400, 4,800, 9,600 or 19,200 bps to operate the SCI properly.
Page 817 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 22-8. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host.
Page 818 The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program.
Page 819 Figure 22-9 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area...
Page 820 22.7 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1 for addresses H'000000 to H'03FFFF.
Page 821 E1 = 1 Erase setup Erase mode state E1 = 0 ESU1 = 1 Normal mode ESU1 = 0 FWE = 1 FWE = 0 Erase-verify EV1 = 1 mode On-board SWE1 = 1 EV1 = 0 Software programming mode programming Software programming enable...
Page 822 Following the elapse of (×0) µs or more after the SWE1 bit is set to 1 in FLMCR1, 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the program data area in RAM is written consecutively to the program address (the lower 8 bits of the first address written to must be H'00 or H'80).
Page 823 4. The write pulse is applied and a flash memory write executed while the P1 bit in FLMCR1 is set. In the H8S/2633, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability.
Page 824 (X'): Data of bits on which reprogramming is executed in a certain reprogramming loop 7. It is necessary to execute additional programming processing during the course of the H8S/2633 program/program-verify procedure. However, once 128-byte-unit programming is finished, additional programming should not be carried out on the same address area. When executing reprogramming, an erase must be executed first.
Page 825 Start of programming Programming must be executed in the erased state. START Do not perform additional programming on addresses that have already been programmed. Set SWE1 bit in FLMCR1 Wait (× 0) µs Write pulse application subroutine tsswe: Sub-Routine Write Pulse Store 128 bytes of program data in program data area and reprogram data area Enable WDT...
Page 826 22.7.3 Erase Mode When erasing flash memory, the single-block erase/erase-verify flowchart shown in figure 22-12 should be followed. To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (EBR1, EBR2) at least (x) µs after setting the SWE1 bit to 1 in FLMCR1.
Page 827 Start Set SWE1 bit in FLMCR1 Wait (x) µs tsswe: n = 1 Set EBR1 and 2 Enable WDT Set ESU1 bit in FLMCR1 Wait (y) µs tsesu: Start erase Set E1 bit in FLMCR1 tse: Wait (z) ms Clear E1 bit in FLMCR1 Halt erase Wait (α) µs tce:...
Page 828 22.8 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 22.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2).
Page 829 22.8.2 Software Protection Software protection can be implemented by setting the SWE1 bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode.
Page 830 22.8.3 Error Protection In error protection, an error is detected when H8S/2633 Series runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing.
Page 831 Figure 22-13 shows the flash memory state transition diagram. Reset or standby Program mode RES = 0 or HSTBY = 0 (hardware protection) Erase mode RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 RES = 0 or Error occurrence HSTBY = 0 FLMCR1, FLMCR2,...
Page 832 22.9 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time.
Page 833 This area can be accessed from both the RAM area and flash memory area H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'FFD000 H'FFDFFF Flash memory EB8 to EB11 On-chip RAM H'FFEFBF H'3FFFF Figure 22-15 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1.
Page 834 22.10 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot mode* , to give priority to the program or erase operation.
Page 835 Table 22-10 Programmer Mode Pin Settings Pin Names Settings Mode pins: MD2, MD1, MD0 Low level input to MD2, MD1, and MD0. Mode setting pins: PF0, P16, P14 High level input to PF0, low level input to P16 and P14 FWE pin High level input (in auto-program and auto-erase modes)
Page 836 HN27C4096HG (40 Pins) H8S/2633 Socket Adapter (Conversion to 40-Pin Pin No. Pin No. Pin Name Arrangement) Pin Name FP-128 TFP-120 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 1, 40 11, 17, 43, 50, 60, 7, 13, 37, 44, 54,...
Page 837 22.11.2 Programmer Mode Operation Table 22-11 shows how the different operating modes are set when using programmer mode, and table 22-12 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. •...
Page 838 Table 22-12 Programmer Mode Commands 1st Cycle 2nd Cycle Number Command Name of Cycles Mode Address Data Mode Address Data Memory read mode 1 + n Write H'00 Read Dout Auto-program mode Write H'40 Write Auto-erase mode Write H'20 Write H'20 Status read mode Write...
Page 839 Command write Memory read mode Address stable A18–A0 nxtc I/O7–I/O0 Note: Data is latched on the rising edge of WE. Figure 22-18 Timing Waveforms for Memory Read after Memory Write Table 22-14 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: V = 3.3 V ±0.3 V, V = 0 V, T...
Page 840 Memory read mode Other mode command write Address stable A18–A0 nxtc I/O7–I/O0 Note: Do not enable WE and OE at the same time. Figure 22-19 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 22-15 AC Characteristics in Memory Read Mode (Conditions: V = 3.3 V ±0.3 V, = 0 V, T = 25°C ±5°C)
Page 841 Address stable Address stable A18–A0 I/O7–I/O0 Figure 22-21 CE and OE Clock System Read Timing Waveforms 22.11.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses.
Page 842 Table 22-16 AC Characteristics in Auto-Program Mode (Conditions: V = 3.3 V ±0.3 V, = 0 V, T = 25°C ±5°C) Item Symbol Unit Command write cycle — µs nxtc CE hold time — CE setup time — Data hold time —...
Page 843 22.11.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4.
Page 844 A18–A0 nxtc nxtc ests erase I/O7 Erase end decision signal I/O6 Erase normal decision signal I/O5–I/O0 H'20 H'20 H'00 Figure 22-23 Auto-Erase Mode Timing Waveforms...
Page 845 22.11.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed.
Page 846 Table 22-19 Status Read Mode Return Commands Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Attribute Normal Command Program- Erase — — Program- Effective error ming error error ming or address error decision erase count exceeded Initial value 0 Indications Normal Command Program-...
Page 847 Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level.
Page 848 (3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or written to. States (2) and (3) are flash memory power-down states. Table 22-22 shows the correspondence between the operating states of the H8S/2633 and the flash memory. Table 22-22 Flash Memory Operating States LSI Operating State...
Page 849 Use a PROM programmer that supports the Hitachi microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter.
Page 850 Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc.
Page 851 Programming/ erasing Wait time: 100 µs possible Wait time: x ø Min 0 µs OSC1 Min 0 µs MD2 to MD0 SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Page 852 Programming/ erasing Wait time: 100 µs possible Wait time: x ø Min 0 µs OSC1 MD2 to MD0 SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Page 853 ø OSC1 Min 0 µs MD2 to MD0 RESW SWE1 SWE1 cleared SWE1 bit Mode Boot Mode User User program mode User User program change mode change mode mode mode Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Page 854 22.14 Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 22-23 lists the registers that are present in the F-ZTAT version but not in the mask ROM version.
Page 855 Section 23 Clock Pulse Generator 23.1 Overview The H8S/2633 Series has a built-in clock pulse generator (CPG) that generates the system clock (ø), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, and waveform shaping circuit.
Page 856 23.1.2 Register Configuration The clock pulse generator is controlled by SCKCR and LPWRCR. Table 23-1 shows the register configuration. Table 23-1 Clock Pulse Generator Register Name Abbreviation Initial Value Address* System clock control register SCKCR H'00 H'FDE6 Low-power control register LPWRCR H'00 H'FDEC...
Page 857 Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS Description Specified multiplication factor is valid after transition to software standby mode, watch mode, and subactive mode (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master...
Page 858 Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit. Bit 1 Bit 0 STC1 STC0 Description ×1 (Initial value) ×2 ×4 Setting prohibited Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should not exceed the maximum operating frequency defined in section 25 Electrical Characteristics.
Page 859 See figure 23-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid Signal A Signal B H8S/2633 Series XTAL EXTAL Figure 23-4 Example of Incorrect Board Design...
Page 860 External circuitry such as that shown below is recommended around the PLL. R1: 3 kΩ C1: 470 pF PLLCAP Rp: 200 Ω PLLVCC CPB: 0.1 µF * PLLVSS PVCC CB: 0.1 µF * CB: 0.1 µF * (Values are recommended values.) Note: * CB and CPB are laminated ceramic capacitors.
Page 861 23.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 23-6. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL External clock input XTAL...
Page 862 External Clock Table 23-4 and figure 23-7 show the input conditions for the external clock. Table 23-4 External Clock Input Conditions = 3.0 V = 3.0 V to 3.6 V, to 3.6 V = 3.0 V = 5.0 V to 5.5 V ±10% Item Symbol...
Page 863 23.4 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC bits in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin.
Page 864 23.7 Subclock Oscillator (1) Connecting 32.768kHz Quartz Oscillator To supply a clock to the subclock oscillator, connect a 32.768kHz quartz oscillator, as shown in Figure 23-8. See Section 23.3.1, Notes on Board Design for notes on connecting crystal oscillators. OSC1 OSC2 =15pF (typ) Figure 23-8 Example Connection of 32.768kHz Crystal Oscillator...
Page 865 (2) Handling pins when subclock not required If no subclock is required, connect the OSC1 pin to Vcc and leave OSC2 open, as shown in Figure 23-10. OSC1 Open OSC2 Figure 23-10 Pin Handling When Subclock Not Required 23.8 Subclock Waveform Shaping Circuit To eliminate noise from the subclock input to OSCI, the subclock is sampled using the dividing clock ø.
Page 866 24.1 Overview In addition to the normal program execution state, the H8S/2633 Series has eight power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.
Page 867 Table 24-1 LSI Internal States in Each Mode High- Medium- Module Sub- Software Hardware Function Speed Speed Sleep Stop Watch active Subsleep Standby Standby System clock pulse Function- Function- Function- Function- Halted Halted Halted Halted Halted generator Subclock pulse Function- Function- Function- Function-...
Page 868 Program-halted state STBY pin = Low Hardware Reset state standby mode STBY pin = High RES pin = Low RES pin = High Program execution state SSBY= 0, LSON= 0 Sleep mode SLEEP command (main clock) High-speed mode (main clock) Any interrupt * SSBY= 1, SLEEP...
Page 869 Table 24.2 Power-Down Mode Transition Conditions State After Transition Status of Control Bit at State After Transition Back from Low Power Transition Pre-Transition Invoked by SLEEP Mode Invoked by State SSBY PSS LSON DTON Command Interrupt High-speed/ Sleep High-speed/Medium-speed Medium-speed 0 —...
Page 870 24.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 24-3 summarizes these registers. Table 24-3 Power-Down Mode Registers Name Abbreviation Initial Value Address* Standby control register SBYCR H'08 H'FDE4 System clock control register SCKCR H'00 H'FDE6...
Page 871 24.2 Register Descriptions 24.2.1 Standby Control Register (SBYCR) SSBY STS2 STS1 STS0 — — — Initial value — — — SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 872 Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode, watch mode, or sub-active mode. With a crystal oscillator (Table 24-5), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency.
Page 873 24.2.2 System Clock Control Register (SCKCR) PSTOP — — — STCS SCK2 SCK1 SCK0 Initial value — — — SCKCR is an 8-bit readable/writable register that performs ø clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control.
Page 874 Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in high-speed mode, medium-speed mode, and sub-active mode. Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode. Bit 2 Bit 1 Bit 0...
Page 875 Bit 7 DTON Description • When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. • When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode.
Page 876 Bit 5—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the sampling frequency of the subclock (øSUB) generated by the subclock oscillator is sampled by the clock (ø) generated by the system clock oscillator. Set this bit to 0 when ø=5MHz or more. Bit 5 NESEL Description...
Page 877 24.2.4 Timer Control/Status Register (TCSR) WDT1 TCSR WT/IT RST/NMI CKS2 CKS1 CKS0 Initial value R/(W)* Note: * Only write 0 to clear the flag. TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode. The following describes bit 4.
Page 878 24.2.5 Module Stop Control Register (MSTPCR) MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control.
Page 879 24.3 Medium-Speed Mode In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0 bits.
Page 880 Medium-speed mode ø, supporting module clock Bus master clock SBYCR SBYCR Internal address bus Internal write signal Figure 24-2 Medium-Speed Mode Transition and Clearance Timing 24.4 Sleep Mode 24.4.1 Sleep Mode When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR LSON bit = 0, the CPU enters the sleep mode.
Page 881 24.5 Module Stop Mode 24.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently.
Page 882 Table 24-4 MSTP Bits and Corresponding On-Chip Supporting Modules Register Module MSTPCRA MSTPA7 DMA controller (DMAC) MSTPA6 Data transfer controller (DTC) MSTPA5 16-bit timer pulse unit (TPU) MSTPA4 8-bit timer (TMR0, TMR1) MSTPA3 Programmable pulse generator (PPG) MSTPA2 D/A converter (channels 0, 1) MSTPA1 A/D converter MSTPA0...
Page 883 24.5.2 Usage Notes DMAC and DTC Module Stop: Depending on the operating status of the DMAC and DTC, the MSTPA7 and MSTPA6 bits may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, DMA Controller and section 9, Data Transfer Controller (DTC).
Page 884 (2) Exiting Software Standby Mode by RES or MRES Pins When the RES pin or MRES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin or MRES pin must be held low until clock oscillation stabilizes.
Page 885 Using an External Clock: The PLL circuit requires a time for stabilization. Insert a wait of 2 ms min. 24.6.4 Software Standby Mode Application Example Figure 24-3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin.
Page 886 In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2633 Series is in hardware standby mode.
Page 887 24.7.2 Hardware Standby Mode Timing Figure 24-4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high.
Page 888 24.8.2 Exiting Watch Mode Watch mode is exited by any interrupt (WOVI1 interrupt, NMI pin, or IRQ0 to IRQ7), or signals at the RES, MRES, or STBY pins. (1) Exiting Watch Mode by Interrupts When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LPWRCR LSON bit = 0 or to sub-active mode when the LSON bit = 1.
Page 889 24.9 Sub-Sleep Mode 24.9.1 Sub-Sleep Mode When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-sleep mode. In sub-sleep mode, the CPU is stopped. Supporting modules other than TMR0 to TMR3, WDT0, and WDT1 are also stopped.
Page 890 24.10 Sub-Active Mode 24.10.1 Sub-Active Mode When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-active mode.
Page 891 24.11 Direct Transitions 24.11.1 Overview of Direct Transitions There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution when shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the LPWRCR DTON bit to 1, then executing the SLEEP instruction.
Page 892 Section 25 Electrical Characteristics 25.1 Absolute Maximum Ratings Table 25-1 lists the absolute maximum ratings. Unless specified otherwise, PV refers to both 1 and PV Table 25-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +4.3 PLLV –0.3 to +7.0 CC1,2...
Page 893 25.2 DC Characteristics Table 25-2 lists the DC characteristics. Table 25-3 lists the permissible output currents. Table 25-2 DC Characteristics (1) Conditions: V = PLLV = 3.0 V to 3.6 V, PV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = 4.5 V to AV = AV = 0 V, T...
Page 894 Test Item Symbol Unit Conditions I  Three-state Port 1, 3, 7, — — µA leakage A to G 0.5 to V – 0.5 current (off state) MOS input Port A to E –I — µA = 0 V pull-up current Input —...
Page 895 Item Symbol Unit Test Conditions Port power Operating — supply = 5.0 V current* Subclock — — µA operation ≤ 50 °C Standby* — 0.01 50 °C < T Watch mode — — Analog During A/D — = 5.0 V power supply and D/A current...
Page 896 Table 25-2 DC Characteristics (2) — Preliminary — Conditions: V = PLLV = 3.0 V to 3.6 V, PV = 3.0 V to 5.5 V, AV = 3.3 V to 5.5 V, = 3.3 V to AV = AV = 0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)*...
Page 897 Item Symbol Min Unit Test Conditions I  Three-state Port 1, 3, 7, — — µA leakage A to G 0.5 to V – 0.5 current (off state) MOS input Port A to E –I — µA = 0 V pull-up current Input —...
Page 898 Item Symbol Min Unit Test Conditions Port power Operating — supply = 5.0 V current* Subclock — — µA operation ≤ 50°C Standby* — 0.01 Watch mode — — 50 °C < T Analog During A/D — = 5.0 V power supply and D/A current...
Page 899 Table 25-3 Permissible Output Currents Conditions: V = PLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AV = 3.3 V to 5.5 V, = 3.3 V to AV = AV = 0 V, T = –20°C to +75°C (regular = –40°C to +85°C (wide-range specifications) * specifications), T...
Page 900 Table 25-4 Bus Drive Characteristics Condition : = PLLV = 3.0 V to 3.6 V, PV = 3.0 V to 5.5 V, AV = 3.3 V to 5.5 V, = 3.3 V to AV = AV = 0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 901 25.3 AC Characteristics Figure 25-1 show, the test conditions for the AC characteristics. LSI output pin C = 50 pF: Ports 10 to 13, 70 to 73, A to G (In case of expansion bus control signal output pin setting) C = 30 pF: All ports = 2.4 kΩ...
Page 902 25.3.1 Clock Timing Table 25-5 lists the clock timing Table 25-5 Clock Timing Condition A: V = PLLV = 3.0 V to 3.6 V, PV = 3.0 V to 5.5 V, AV = 3.3 V to 5.5 V, = 3.3 V to AV = AV = 0 V, ø...
Page 903 ø Figure 25-2 System Clock Timing EXTAL DEXT DEXT STBY OSC1 OSC1 ø Figure 25-3 Oscillator Settling Timing...
Page 904 25.3.2 Control Signal Timing Table 25-6 lists the control signal timing. Table 25-6 Control Signal Timing Condition A: V = PLLV = 3.0 V to 3.6 V, PV = 3.0 V to 5.5 V, AV = 3.3 V to 5.5 V, = 3.3 V to AV = AV = 0 V, ø...
Page 905 ø RESS RESS MRESS MRESS RESW MRES MRESW Figure 25-4 Reset Input Timing ø NMIS NMIH NMIW IRQW IRQS IRQH Edge input IRQS Level input Figure 25-5 Interrupt Input Timing...
Page 906 25.3.3 Bus Timing Table 25-7 lists the bus timing. Table 25-7 Bus Timing Condition A: V = PLLV = 3.0 V to 3.6 V, PV = 3.0 V to 5.5 V, AV = 3.3 V to 5.5 V, = 3.3 V to AV = AV = 0 V, ø...
Page 907 Condition A Condition B Test Item Symbol Unit Conditions 3.0 × 3.0 × Read data access — — Figure 25-6 to ACC5 time 5 Figure 25-11 – 35 – 25 WR delay time 1 — — WRD1 WR delay time 2 —...
Page 908 ø A23 to A0 CSD1 CS7 to CS0 RSD2 RSD1 ACC2 (read) ACC3 D15 to D0 (read) WRD2 WRD2 (write) WSW1 D15 to D0 (write) Figure 25-6 Basic Bus Timing (Two-State Access)
Page 909 ø A23 to A0 CSD1 CS7 to CS0 RSD1 ACC4 RSD2 (read) ACC5 D15 to D0 (read) WRD1 WRD2 (write) WSW2 D15 to D0 (write) Figure 25-7 Basic Bus Timing (Three-State Access)
Page 910 ø A23 to A0 CS7 to CS0 (read) D15 to D0 (read) (write) D15 to D0 (write) WAIT Figure 25-8 Basic Bus Timing (Three-State Access with One Wait State)
Page 911 or T ø A23 to A0 CS7 to CS0 RSD2 (read) ACC3 D15 to D0 (read) Figure 25-9 Burst ROM Access Timing (Two-State Access)
Page 912 or T ø A23 to A0 CS7 to CS0 RSD2 (read) ACC1 D15 to D0 (read) Figure 25-10 Burst ROM Access Timing (One-State Access)
Page 913 ø A23 to A0 ACC4 CS5 to CS2 (RAS) CSD2 CASD1 ACC1 CASD1 CAL, LCAS (RCTS=0) CASD2 ACC2 CASD1 CAL to LCAS (When RCTS is set to 1) (read) OED2 ACC2 OED1 (When OES is set to 1) (read) ACC3 D15 to D0 (read) WRD1...
Page 914 ø CSD2 CSD2 CS5 to CS2 (RAS) CASD1 CASD1 CAS, LCAS Figure 25-13 DRAM Self-Refresh Timing ø BRQS BRQS BREQ BACD BACD BACK A23 to A0 CS7 to CS0, AS, RD, HWR, LWR Figure 25-14 External Bus Release Timing ø BRQOD BRQOD BREQO...
Page 915 25.3.4 DMAC Timing Table 25-8 shows the DMAC timing. Table 25-8 DMAC Timing Condition A: V = PLLV = 3.0 V to 3.6 V, PV = 3.0 V to 5.5 V, AV = 3.3 V to 5.5 V, = 3.3 V to AV = AV = 0 V, ø...
Page 916 ø A23 to A0 CS7 to CS0 (read) D15 to D0 (read) HWR to LWR D15 to D0 (write) DACD1 DACD2 DACK0, DACK1 Figure 25-16 DMAC Single Address Transfer Timing / Two-State Access...
Page 917 ø A23 to A0 CS7 to CS0 (read) D15 to D0 (read) HWR to LWR D15 to D0 (write) DACD1 DACD2 DACK0, DACK1 Figure 25-17 DMAC Single Address Transfer Timing / Three-State Access ø TEND0, TEND1 Figure 25-18 DMAC TEND Output Timing...
Page 918 ø DRQS DRQH DREQ0, DREQ1 Figure 25-19 DMAC DREQ Input Timing...
Page 919 25.3.5 Timing of On-Chip Supporting Modules Table 25-9 lists the timing of on-chip supporting modules. Table 25-9 Timing of On-Chip Supporting Modules Condition A: V = PLLV = 3.0 V to 3.6 V, PV = 3.0 V to 5.5 V, AV = 3.3 V to 5.5 V, = 3.3 V to AV = AV...
Page 920 Condition A Condition B Item Symbol Unit Test Conditions Timer output delay — — Figure 25-24 TMOD time Timer reset input — — Figure 25-26 TMRS setup time Timer clock input — — Figure 25-25 TMCS setup time Timer Single —...
Page 921 ø Port 1, 3, 4, 7, 9 A to G (read) Port 1, 3, 7 A to G (write) Figure 25-20 I/O Port Input/Output Timing ø PO 15 to 8 Figure 25-21 PPG Output Timing ø TOCD Output compare output * TICS Input capture input*...
Page 922 ø TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 25-23 TPU Clock Input Timing ø TMOD TMO0, TMO1 TMO2, TMO3 Figure 25-24 8-bit Timer Output Timing ø TMCS TMCS TMCI01, TMCI23 TMCWL TMCWH Figure 25-25 8-bit Timer Clock Input Timing ø...
Page 923 ø WOVD WOVD WDTOVF Figure 25-27 WDT0 Output Timing ø BUZD BUZD BUZZ Figure 25-28 WDT1 Output Timing ø PWOD PWM3 toPWM0 Figure 25-29 PWM Output Timing SCKW SCKr SCKf SCK0 to SCK4 Scyc Figure 25-30 SCK Clock Input Timing...
Page 924 SCK0 to SCK4 TxD0 to TxD4 (transit data) RxD0 to RxD4 (receive data) Figure 25-31 SCI Input/Output Timing (Clock Synchronous Mode) ø TRGS ADTRG Figure 25-32 A/D Converter External Trigger Input Timing...
Page 925 Table 25-10 I C Bus Timing Conditions: V = PLV = 3.0 V to 3.6 V, PV = 3.0 V to 5.5 V, V = 0 V, ø = 5 MHz to maximum operating frequency, T = –20°C to +75°C Ratings Item Symbol...
Page 926 SDA0 SDA1 SCLH STOS STAH STAS SCL0 SCL1 SCLL SDAS SDAH Note: S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition Figure 25-33 I C Bus Inteface Input/Output Timing (Option)
Page 927 25.4 A/D Conversion Characteristics Table 25-11 lists the A/D conversion characteristics. Table 25-11 A/D Conversion Characteristics Condition A: V = PLLV = 3.0 V to 3.6 V, PV = 3.0 V to 5.5 V, AV = 3.3 V to 5.5 V, = 3.3 V to AV = AV = 0 V, ø...
Page 928 25.5 D/A Conversion Characteristics Table 25-12 shows the D/A conversion characteristics. Table 25-12 D/A Conversion Characteristics Condition A: V = PLLV = 3.0 V to 3.6 V, PV = 3.0 V to 5.5 V, AV = 3.3 V to 5.5 V, = 3.3 V to AV = AV = 0 V, ø...
Page 929 25.6 Flash Memory Characteristics Table 25-14 Flash Memory Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 4.5 V to 5.5 V, V = AV = 0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Min Unit...
Page 930 3. Time to erase one block. (Indicates the time during which the E1 bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time (t P (max) = Wait time after P1 bit setting (z) × maximum number of writes (N)) (z0 + z1) ×...
Page 931 Appendix A Instruction Set Instruction List Operand Notation General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-and-accumulate register (32-bit register) (EAd) Destination operand (EAs) Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
Page 932 Condition Code Notation Symbol Changes according to the result of instruction Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 — Not affected by execution of the instruction...
Page 955 Instruction Codes Table A-2 shows the instruction codes.
Page 970 Operation Code Map Table A-3 shows the operation code map.
Page 974 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle.
Page 975 Table A-4 Number of States per Cycle Access Conditions External Device On-Chip Supporting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2m 3 + m Branch address read S Stack operation Byte data access 3 + m...
Page 976 Table A-5 Number of Cycles in Instruction Execution Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1/2/4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd...
Page 977 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16...
Page 978 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8...
Page 979 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16...
Page 980 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16...
Page 981 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic EEPMOV EEPMOV.B 2n+2* EEPMOV.W 2n+2* EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn...
Page 982 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd...
Page 983 MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @:aa:16,Rd Can not be used in the H8S/2633 Series MOVTPE MOVTPE Rs,@:aa:16 MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd...
Page 984 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd...
Page 985 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd 2/3* SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR...
Page 986 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) 3 STC.W EXR,@(d:16,ERd) 3 STC.W CCR,@(d:32,ERd) 5 STC.W EXR,@(d:32,ERd) 5 STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32...
Page 987 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2.
Page 988 Bus States During Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle. How to Read the Table: Order of execution Instruction Internal operation, JMP@aa:24 R:W 2nd R:W EA...
Page 989 Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. ø Address bus HWR, LWR High level Internal R:W 2nd R:W EA...
Page 1002 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. 31 for longword operands 15 for word operands 7 for byte operands The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand...
Page 1003 Table A-7 Condition Code Modification Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
Page 1004 Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
Page 1005 Definition — — N = Rm Z = Rm · Rm–1 · ..· R0 MOVFPE Can not be used in H8S/2633 Series MOVTPE MULXS — — — N = R2m Z = R2m · R2m–1 · ..· R0 MULXU —...
Page 1006 Instruction Definition ROTXL — N = Rm Z = Rm · Rm–1 · ..· R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — N = Rm Z = Rm · Rm–1 · ..· R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) Stores the corresponding bits of the result.
Page 1007 Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
Page 1008 Appendix B Internal I/O Register Addresses Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width (bits) H'FDAC DADR2 D/A2, D/A3 H'FDAD DADR3 H'FDAE DACR23 DAOE1 DAOE0 DAE —...
Page 1009 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width (bits) H'FDD4 SSR3 TDRE RDRF ORER TEND MPBT SCI3, Smart SSR3 TDRE RDRF ORER TEND MPBT card H'FDD5 RDR3...
Page 1010 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width (bits) H'FE16 DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 H'FE17 DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 H'FE18 DTCERC DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 H'FE19 DTCERD...
Page 1011 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width (bits) H'FE80 TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU3 H'FE81 TMDR3 — — H'FE82 TIOR3H IOB3 IOB2...
Page 1012 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width (bits) H'FEB0 TSTR — — CST5 CST4 CST3 CST2 CST1 CST0 H'FEB1 TSYR — — SYNC5 SYNC4 SYNC3 SYNC2...
Page 1013 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width (bits) H'FEEC IOAR0B DMAC H'FEED H'FEEE ETCR0B H'FEEF H'FEF0 MAR1AH — — — — — — —...
Page 1014 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width (bits) H'FF12 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TPU0 H'FF13 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3...
Page 1015 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width (bits) H'FF3A TGR2B TPU2 H'FF3B H'FF60 DMAWER — — — — WE1B WE1A WE0B WE0A DMAC H'FF61 DMATCR —...
Page 1016 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width (bits) H'FF7C SSR0 TDRE RDRF ORER TEND MPBT SCI0, IIC0, Smart card SSR0 TDRE RDRF ORER TEND MPBT interface...
Page 1017 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width (bits) H'FF93 ADDRBL — — — — — — H'FF94 ADDRCH AD9 H'FF95 ADDRCL — — —...
Page 1018 Functions DADR0—D/A Data Register 0 H'FFA4 D/A0 DADR1—D/A Data Register 1 H'FFA5 D/A1 DADR2—D/A Data Register 2 H'FDAC D/A2 DADR3—D/A Data Register 3 H'FDAD D/A3 Initial value DACR01—D/A Control Register 01 H'FFA6 D/A0, 1 DACR23—D/A Control Register 23 H'FDAE D/A2, 3 DAOE1 DAOE0 —...
Page 1019 IrCR—IrDA Control Register H'FDB0 SCI0, IrDA Ir E IrCKS2 IrCKS1 IrCKS0 — — — — Initial value — — — — IrDA clock select 2 to 0 Bit 6 Bit 5 Bit 4 Description IrCKS2 IrCKS1 IrCKS0 B × 3/16 (3/16ths of bit rate) ø/2 ø/4 ø/8...
Page 1020 DDCSWR—DDC Switch Register H'FDB5 — — — — CLR3 CLR2 CLR1 CLR0 Initial value R/(W)* R/(W)* R/(W)* R/(W)* Reserved bit IIC clear 3 to 0 CLR3 CLR2 CLR1 CLR0 — — Setting prohibited Setting prohibited IIC0 internal latch cleared IIC1 internal latch cleared IIC0 and IIC1 internal latch cleared Invalid setting —...
Page 1021 DACR0—PWM (D/A) Control Register 0 H'FDB8 PWM0 DACR1—PWM (D/A) Control Register 1 H'FDBC PWM1 TEST PWME — — Initial value — — Clock select 0 Resolution (T) = system clock cycle (tcyc). 1 Resolution (T) = system clock cycle (tcyc) × 2. Output select 0 Direct PWM output.
Page 1022 DADRAH0—PWM (D/A) Data Register AH0 H'FDB8 PWM0 DADRAL0—PWM (D/A) Data Register AL0 H'FDB9 PWM0 DADRBH0—PWM (D/A) Data Register BH0 H'FDBA PWM0 DADRBL0—PWM (D/A) Data Register BL0 H'FDBB PWM0 DADRAH1—PWM (D/A) Data Register AH1 H'FDBC PWM1 DADRAL1—PWM (D/A) Data Register AL1 H'FDBD PWM1 DADRBH1—PWM (D/A) Data Register BH1...
Page 1023 DACNTH0—PWM (D/A) Counter H0 H'FDBA PWM0 DACNTL0—PWM (D/A) Counter L0 H'FDBB PWM0 DACNTH1—PWM (D/A) Counter H1 H'FDBE PWM1 DACNTL1—PWM (D/A) Counter L1 H'FDBF PWM1 DACNTH DACNTL Bit (CPU) Bit (counter) — — REGS Initial value — Register select 0 DADRA and DADRB access enabled 1 DACR and DACNT access enabled 1011...
Page 1024 TCR0—Timer Control Register 0 H'FF68 TMR0 TCR1—Timer Control Register 1 H'FF69 TMR1 TCR2—Timer Control Register 2 H'FDC0 TMR2 TCR3—Timer Control Register 3 H'FDC1 TMR3 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Timer overflow interrupt enable OVF interrupt request (OVI) disabled OVF interrupt request (OVI) enabled Compare match interrupt enable A CMFA interrupt request (CMIA) disabled...
Page 1025 TCSR0—Timer Control/Status Register 0 H'FF6A TMR0 TCSR1—Timer Control/Status Register 1 H'FF6B TMR1 TCSR2—Timer Control/Status Register 2 H'FDC2 TMR2 TCSR3—Timer Control/Status Register 3 H'FDC3 TMR3 TCSR0 CMFB CMFA ADTE Initial value R/(W) * R/(W) * R/(W) * TCSR1, TCSR3 CMFB CMFA —...
Page 1026 TCORA0—Time Constant Register A0 H'FF6C TMR0 TCORA1—Time Constant Register A1 H'FF6D TMR1 TCORA2—Time Constant Register A2 H'FDC4 TMR2 TCORA3—Time Constant Register A3 H'FDC5 TMR3 TCORA0 (TCORA2) TCORA1 (TCORA3) Initial value TCORB0—Time Constant Register B0 H'FF6E TMR0 TCORB1—Time Constant Register B1 H'FF6F TMR1 TCORB2—Time Constant Register B2...
Page 1027 SMR0—Serial Mode Register 0 H'FF78 SCI0 SMR1—Serial Mode Register 1 H'FF80 SCI1 SMR2—Serial Mode Register 2 H'FF88 SCI2 SMR3—Serial Mode Register 3 H'FDD0 SCI3 SMR4—Serial Mode Register 4 H'FDD8 SCI4 STOP CKS1 CKS0 Initial value Clock select 1 and 0 CKS1 CKS0 Description ø...
Page 1028 SMR0—Serial Mode Register 0 H'FF78 Smart Card SMR1—Serial Mode Register 1 H'FF80 Interface SMR2—Serial Mode Register 2 H'FF88 SMR3—Serial Mode Register 3 H'FDD0 SMR4—Serial Mode Register 4 H'FDD8 BCP1 BCP0 CKS1 CKS0 Initial value Basic clock pulse 1, 0 BCP1 BCP0 32 clock 64 clock 372 clock...
Page 1029 BRR0—Bit Rate Register 0 H'FF79 SCI0 BRR1—Bit Rate Register 1 H'FF81 SCI1 BRR2—Bit Rate Register 2 H'FF89 SCI2 BRR3—Bit Rate Register 3 H'FDD1 SCI3 BRR4—Bit Rate Register 4 H'FDD9 SCI4 Initial value 1017...
Page 1030 SCR0—Serial Control Register 0 H'FF7A SCI0 SCR1—Serial Control Register 1 H'FF82 SCI1 SCR2—Serial Control Register 2 H'FF8A SCI2 SCR3—Serial Control Register 3 H'FDD2 SCI3 SCR4—Serial Control Register 4 H'FDDA SCI4 MPIE TEIE CKE1 CKE0 Initial value Clock enable 1, 0 Bit 1 Bit 0 Description...
Page 1031 TDR0—Transmit Data Register 0 H'FF7B SCI0 TDR1—Transmit Data Register 1 H'FF83 SCI1 TDR2—Transmit Data Register 2 H'FF8B SCI2 TDR3—Transmit Data Register 3 H'FDD3 SCI3 TDR4—Transmit Data Register 4 H'FDDB SCI4 Initial value 1019...
Page 1032 SSR0—Serial Status Register 0 H'FF7C SCI0 SSR1—Serial Status Register 1 H'FF84 SCI1 SSR2—Serial Status Register 2 H'FF8C SCI2 SSR3—Serial Status Register 3 H'FDD4 SCI3 SSR4—Serial Status Register 4 H'FDDC SCI4 TDRE RDRF ORER TEND MPBT Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor bit transfer...
Page 1033 RDR0—Receive Data Register 0 H'FF7D SCI0 RDR1—Receive Data Register 1 H'FF85 SCI1 RDR2—Receive Data Register 2 H'FF8D SCI2 RDR3—Receive Data Register 3 H'FDD5 SCI3 RDR4—Receive Data Register 4 H'FDDD SCI4 Initial value SCMR0—Smart Card Mode Register 0 H'FF7E SCI0 SCMR1—Smart Card Mode Register 1 H'FF86 SCI1 SCMR2—Smart Card Mode Register 2...
Page 1034 SBYCR—Standby Control Register H'FDE4 System SSBY STS2 STS1 STS0 — — — Initial value — — — Output port enable 0 In software standby mode, watch mode, and during direct transfer, the address bus and bus control signal are in the high-impedance state. 1 In software standby mode, watch mode, and during direct transfer, the address bus and bus control signal remain in the output state.
Page 1035 SYSCR—System Control Register H'FDE5 System MACS — INTM1 INTM0 NMIEG MRESE — RAME Initial value — — NMI edge select Interrupt request issued on falling edge of NMI input. Interrupt request issued on rising edge of NMI input. Interrupt control mode 1, 0 Interrupt INTM1 INTM0...
Page 1036 SCKCR—System Clock Control Register H'FDE6 System PSTOP — — — STCS SCK2 SCK1 SCK0 Initial value — — — System clock select 2 to 0 SCK2 SCK1 SCK0 Bus master set to high-speed mode. Medium-speed clock: ø/2 Medium-speed clock: ø//4 Medium-speed clock: ø8 Medium-speed clock: ø/16 Medium-speed clock: ø/32...
Page 1037 MDCR—Mode Control Register H'FDE7 System — — — — — MDS2 MDS1 MDS0 Initial value —* —* —* — — — — Mode select 2 to 0 Note: * Determined by pins MD2 to MD0. MSTPCRA—Module Stop Control Register A H'FDE8 System MSTPA7...
Page 1038 MSTPCRC—Module Stop Control Register C H'FDEA System MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value Module stop PC brake controller module stop mode canceled. PC brake controller module stop mode enabled. 1026...
Page 1039 PFCR—Pin Function Control Register H'FDEB System CSS07 CSS36 BUZZE LCASS Initial value Initial value LCAS output pin select bit LCAS signal output from PF2. LCAS signal output from PF6. BUZZ output enable Functions as PF1 input pin. Functions as BUZZ output pin. CS3/CS6 Select Selects CS3.
Page 1040 LPWRCR—Low-Power Control Register H'FDEC System DTON LSON NESEL SUBSTP RFCUT — STC1 STC0 Initial value Initial value Frequency multiplier STC1 STC0 × 1 (initial value) × 2 × 4 Do not set. Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should not exceed the maximum operating frequency defined in section 25 Electrical Characteristics.
Page 1041 BARA—Break Address Register A H'FE00 BARB—Break Address Register B H'FE04 ··· ··· — ··· — ··· Initial value Unde- Unde- ··· ··· fined fined — ··· — ··· Break address 23 to 0 Note: The bit configuration of BARB is the same as that of BARA. 1029...
Page 1042 BCRA—Break Control Register A H'FE08 BCRB—Break Control Register B H'FE09 CMFA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA Initial value R/(W)* CPU cycle/DTC cycle select A When the CPU is the bus master, PC break performed. When the CPU or DTC is the bus master, PC break performed. Condition match flag A [Clearing] Writing 0 to CMFA after reading CMFA=1.
Page 1043 ISCRH—IRQ Sense Control Register H H'FE12 Interrupt Controller ISCRL—IRQ Sense Control Register L H'FE13 Interrupt Controller ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value IRQ7 sense control A, B to IRQ0 sense control A, IRQ7SCB IRQ7SCA...
Page 1044 ISR—IRQ Status Register H'FE15 Interrupt Controller IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* IRQ7 to IRQ0 flag [Clearing] (1) Writing 0 to flag IRQnF after reading IRQnF=1; (2) When interrupt exception processing is executed when set for LOW-level detection (IRQnSCB=IRQnSCA=0) and, in addition, the IRQn input level is HIGH;...
Page 1045 DTCER—DTC Enable Register H'FE16 H'FE1E DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial value DTC start enable DTCEn DTC startup by interrupt disabled [Clearing] • When data transmission ends with the DISEL bit =1. • On completion of the specified number of transmissions. DTC startup by interrupt enabled [Retention] When DISEL=0 and the specified number of transmissions has not completed.
Page 1046 DTVECR—DTC Vector Register H'FE1F SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* DTC software startup enable DTC software startup disabled [Clearing] • When DISEL=0 and the specified number of transmissions has not completed.
Page 1047 PCR—PPG Output Control Register H'FE26 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Group 2 compare match select 1, 0 G2CMS1 G2CMS0 Pulse output group 2 output trigger TPU channel 0 compare match TPU channel 1 compare match TPU channel 2 compare match TPU channel 3 compare match Group 3 compare match select 1, 0...
Page 1048 PMR—PPG Output Mode Register H'FE27 G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value Group 0 inversion Pulse output group 0 set for inverted output (pin output level is set LOW when PODRL=1). Pulse output group 0 set for direct output (pin output level is set HIGH when PODRL=1).
Page 1049 NDERH—Next Data Enable Register H H'FE28 NDERL—Next Data Enable Register L H'FE29 NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Next data enable 15 to 8 NDER15 to NDER8 Pulse output PO15 to PO8 disabled (transfer from NDR15-NDR8 to POD15-POD8 disabled).
Page 1050 PODRH—Output Data Register H H'FE2A PODRL—Output Data Register L H'FE2B PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial value R/(W)* R/(W)* R/(W)*...
Page 1051 NDRH—Next Data Register H H'FE2C, H'FE2E Same trigger for pulse output groups. NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value — — — — — — — — Initial value — — — — — — — — Different triggers for pulse output groups.
Page 1052 NDRL—Next Data Register L H'FE2D, H'FE2F Same trigger for pulse output groups. NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value — — — — — — — — Initial value — — — — — — — — Different triggers for pulse output groups.
Page 1053 P3DDR—Port 3 Data Direction Register H'FE32 Port P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value P7DDR—Port 7 Data Direction Register H'FE36 Port P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Initial value PADDR—Port A Data Direction Register H'FE39 Port —...
Page 1054 PDDDR—Port D Data Direction Register H'FE3C Port PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value PEDDR—Port E Data Direction Register H'FE3D Port PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value PFDDR—Port F Data Direction Register H'FE3E Port PF7DDR PF6DDR...

This manual is also suitable for:

Hd6432633 Hd6432631 Hd64f2633 H8s/2632 Hd6432632 H8s/2631