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DRAMCR—DRAM Control Register
Bit
:
RFSHE
Initial value
:
R/W
:
1072
7
6
CBRM
RMODE
0
0
R/W
R/W
Refresh mode
0
1
CBR refresh mode
0
External access enabled at CAS-before-RAS refresh.
1
External access disabled at CAS-before-RAS refresh.
Refresh control
0
Do not perform refresh control.
1
Perform refresh control.
Compare match flag
0
[Clearing]
Writing 0 to CMF flag after reading CMF=1.
1
[Setting]
When RTCNT=RTCOR.
Compare match interrupt enable
5
4
CMF
0
0
R/W
R/W
Do not perform self-refresh in software standby
mode.
Perform self-refresh in software standby mode.
0
CMF flag interrupt request (CMI) disabled.
1
CMF flag interrupt request (CMI) enabled.
Refresh counter clock select
CKS2
CKS1
0
0
1
1
0
1
H'FED7
3
2
CMIE
CKS2
0
0
R/W
R/W
CKS0
0
No counting operation
1
Counting on ø/2
0
Counting on ø/8
1
Counting on ø/32
0
Counting on ø/128
1
Counting on ø/512
0
Counting on ø/2048
1
Counting on ø/4096
Bus Controller
1
0
CKS1
CKS0
0
0
R/W
R/W
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