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TCR0—Timer Control Register 0
TCR3—Timer Control Register 3
Channel 0: TCR0
Channel 3: TCR3
Bit
Initial value
R/W
Counter clear 2, 1, 0
CCLR2
0
1
Note: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer
1046
:
7
6
CCLR2
CCLR1
:
0
0
:
R/W
R/W
Clock edge 1, 0
CKEG1
CKEG0
0
0
Counts on rising edge.
1
Counts on falling edge.
1
—
Counts on both edges.
Note: * Internal clock edge selection is valid only when the input clock is ø/4 or slower. This
setting is ignored when the input clock is ø/1 or an overflow or underflow in another
channel is selected.
CCLR1
CCLR0
0
0
TCNT clearing disabled.
1
TCNT cleared at TGRA compare match/input capture.
1
0
TCNT cleared at TGRB compare match/input capture.
1
TCNT cleared when other channel counters with synchronized
clearing or synchronized operation are cleared.*
0
0
TCNT clearing disabled.
1
TCNT cleared at TGRC compare match/input capture.*
1
0
TCNT cleared at TGRD compare match/input capture.*
1
TCNT cleared when other channel counters with synchronized
clearing or synchronized operation are cleared. *
register setting has priority, and compare match/input capture does not occur.
H'FF10
H'FE80
5
4
3
CCLR0
CKEG1
CKEG0
0
0
0
R/W
R/W
R/W
Time prescaler 2, 1, 0
TCR0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
TCR3
0
0
0
1
1
0
1
1
0
0
1
1
0
1
2
1
TPSC2
TPSC1
0
0
R/W
R/W
Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
Internal clock: counts on ø/1024
Internal clock: counts on ø/256
Internal clock: counts on ø/4096
1
2
2
1
TPU0
TPU3
0
TPSC0
0
R/W
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