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TIOR5—Timer I/O Control Register 5
Bit
:
IOB3
Initial value
:
R/W
:
R/W
TGR5B I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
*
0
0
1
1
*
1050
7
6
IOB2
IOB1
0
0
R/W
R/W
TGR5A I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
1
*
1
1
*
TGR5B is
Output disabled
output
Initial output is 0
compare
output
register
Output disabled
Initial output is 1
output
TGR5B is
Capture input
input
source is
capture
TIOCB5 pin
register
H'FEA2
5
4
IOB0
IOA3
0
0
R/W
R/W
TGR5A is
Output disabled
output
Initial output is 0
compare
output
register
Output disabled
Initial output is 1
output
TGR5A is
Capture input
input
source is
capture
TIOCA5 pin
register
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
3
2
IOA2
IOA1
0
0
R/W
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
*: Don't care
TPU5
1
0
IOA0
0
0
R/W
*: Don't care
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