Table of Contents
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Instruction,
Details,4-18ff
Execution Overlap, 8-4
Execution Time Calculation, 8-6
Fetch Signal (IFETCH), 7-32
Format, 4-3
Format Summary, 4-175
M68000 Family Compatibility, 4-1
New, 4-2
Pipe, 8-2, 7-32
Pipe Signal (IPIPE), 7-32
Summary, 4-6
Timing Tables, 8-11
Traps, 6-9
Instruction Set Extensions, A-3
Instruction Stream Timing Examples, 8-8
Instructions,
Binary-Coded Decimal (BCD), 4-13, 8-21
Bit Manipulation, 4-12, 8-24
Conditional Branch, 4-14, 8-25
Data Movement, 4-8,8-16
Exception Related, 4-15, 8-27
Integer Arithmetic, 4-9, 8-18
Logic, 4-11, 8-18
Program Control (Branch), 4-14, 8-25
Shift and Rotate, 4-11, 8-23
Single Operand, 8-19
System Control, 4-15, 8-27
Table Lookup and Interpolation, 4-195
Interrupts, 6-14
- L -
Logic Instructions, 4-11
Low-Power Stop (LPSTOP), 4-2, 5-1
-M-
M68000 Family Addressing Capability, 3-18
M68000 Family Compatibility, 4-1
Memory,
Addressing Modes, 3-4
Indirect Addressing, 3-5ff
Organization, 2-7
Virtual,1-2
Microbus Controller, 8-4
Microsequencer, 8-1
Model, Programming, 2-1
Move Instruction Timing, 8-14
Move Instruction, Special Purpose, Timing, 8-15
Multiple Exceptions, 6-4
- N -
CPU32 REFERENCE MANUAL
INDEX
Negative Tails, 8-7
Organization in Memory, 2-7
Notation, Instruction Set, 4-4
Notation Conventions, Addressing, 3-2
Normal Processing State, 5-1
- 0 -
Opcode Tracking during Loop Mode, 7-34
Opcode Tracking in Background Mode, 7-2, 7-32
Organ ization,
Memory, 2-7
Registers, 2-4
Overlap, 8-4
- p -
Pipe-line Sync with the NOP Instruction, 4-203
Prefetch Controller, 8-3
Priority,
Exception, 6-4
Interrupt, 6-14
Privilege Levels, 5-2
Changing, 5-3
Supervisor, 5-2
User, 5-2
Privilege Violations, 6-12
Processing of Specific Exceptions, 6-6
Processing States, 5-1
Program and Data References, 3-2, 5-3
Program Control (Branch) Instructions, 4-14
Program Counter Indirect with Displacement Mode, 3-8
Index (8-Bit Displacement), 3-9
Index (Base Displacement), 3-9
Programming Model, 2-1
Programming View of Addressing Modes, 3-13
- Q -
Queues, 3-21
-R-
MOTOROLA
3
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