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8.3.6 Immediate Arithmetic/Logic Instructions
The immediate arithmetic/logic instruction table indicates the number of clock
periods needed for the processor to fetch the source immediate data value and
to perform the specified arithmetical/logical instruction using the specified
addressing mode. Footnotes indicate when to account for the appropriate fetch
effective or fetch immediate effective address times. The total number of clock
cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock
reads and writes.
MOTOROLA
8-20
Instruction
Head
Tall
Cycles
MOVEQ
#, Dn
0
0
2(0/1/0)
ADDQ
#, Rn
0
0
2(0/1/0)
ADDQ
#, (FEA)
0
3
5(0/1/x)
SUBQ
#,Rn
0
0
2(0/1/0)
SUBQ
#, (FEA)
0
3
5(0/1 Ix)
ADDI
#, Rn
0
0
2(0/1/0)*
ADDI
#, (FEA)
0
3
5(0/1/x)*
ANDI
#,Rn
0
0
2(0/1/0)*
ANDI
#, (FEA)
0
3
5(0/1/x)*
EORI
#,Rn
0
0
2(0/1/0)*
EORI
#, (FEA)
0
3
5(0/1/x)*
ORI
#,Rn
0
0
2(0/1/0)*
ORI
#, (FEA)
0
3
5(0/1/x)*
SUBI
#,Rn
0
0
2(0/1/0)*
SUBI
#, (FEA)
0
3
5(0/1/x)*
CMPI
#, Rn
0
0
2(0/1/0)*
CMPI
#, (FEA)
0
3
5(0/1/x)*
X
=
There is one bus cycle for byte and word operands and two bus cycles for long
operands. For long bus cycles, add two clocks to the tail and to the number of
cycles.
*
An # fetch effective add ress time must be added for this instruction:
(FEA) +(FEA) + (OPER).
INSTRUCTION EXECUTION
CPU32 REFERENCE MANUAL
TIMING
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