Motorola CPU32 Reference Manual page 261

Table 5-1. Address Spaces
FC2 FC1 FCO
Address Space
0 0
0
Undefined Reserved*
0 0 1 User Data Space
0
1 0 User Program Space
0
1 1
Undefined Reserved*
1
0
0
Undefined Reserved*
1 0 1 Supervisor Data Space
1 1 0 Supervisor Program Space
1 1 1 CPU Space
*Address space 3 is reserved for user definition;
o
and 4 are reserved for future use
by
Motorola.
Although an appropriate address space is selected, memory locations of user
program and data , and of supervisor data, within that address space are not
predefined. During reset, two long words beginning at memory location zero in
the supervisor program space are used for processor initialization. No other
memory locations are explicitly defined by the CPU32.
5.3.1 CPU Space Access
Function code $7 ([FC2:FCO]
=
111) selects CPU address space. The
processor communicates with external devices for special purposes by
accessing this space. All M68000 processors use CPU space for interrupt
acknowledge cycles. The CPU32 also uses CPU space for breakpoint
acknowledge and the LPSTOP broadcast.
Supervisor programs can use the MOVES instruction to access all address
spaces, including user spaces and CPU address space. Although the MOVES
instruction can be used to generate CPU space cycles, doing so may interfere
with proper system operation. Exercise caution when using MOVES to access
CPU space.
Address bus encoding facilitates CPU space transactions. Bits A[19:16], the
CPU space type field, show which transaction is being performed. Currently,
only five of the 16 possible encodings are defined: 0000, 0001, 0010, 0011, and
1111. Of these, only 0000, 0011, and 1111 are supported by the CPU32.
Address bits A[31 :20] are not present on all M68000 processors, and thus
cannot be essential to CPU space transaction decoding. The function of other
address bus bit fields depends on the transaction being performed. A
description of each defined CPU space types follows.
MOTOROLA
5-4
PROCESSING STATES CPU32 REFERENCE MANUAL