Motorola CPU32 Reference Manual page 337

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8.2.3 Timing Example 3: Negative Tails
This example (Figure 8-7) shows how to use negative tail figures for branches
and other change-of-flow instructions. In this example, bus speed is assumed
to be four clocks per access. Instruction three is at the branch destination.
Instructions
MOVEQ
BRA.W
MOVE.L
#7,01
FARAWAY
01,00
Although the CPU32 has a two-word instruction pipeline, internal delay causes
minimum branch instruction time to be three bus cycles. The negative tail is a
reminder that an extra two clocks are available for prefetching a third word on a
fast bus - on a slower bus, there is no extra time for the third word.
2 4 5
CLOCK
BUS
CONTROLLER
INSTRUCTION
MOVE
CONTROLLER
TODD
EXECUTION
TIME
Figure 8-7. Example 3 -
Branch Negative Tail
Example 3 illustrates three different aspects of instruction time calculation:
The branch instruction does not attempt to prefetch beyond the minimum
number of words needed for itself.
The negative tail allows execution to begin sooner than would a three-word
pipeline.
There is a one-clock delay due to late arrival of the displacement at the CPU.
Only changes of flow require negative tail calculation, but the concept can be
generalized to any instruction - only two words are required to be in the
pipeline, but up to three words may be present. When there is an opportunity
for an extra prefetch, it is made. A prefetch to replace an instruction can begin
ahead of the instruction, resulting in a faster processor.
MOTOROLA
8-10
INSTRUCTION EXECUTION CPU32 REFERENCE MANUAL
TIMING