Addition and Subtraction Instructions............... 5-3 Binary Coded Decimal Instructions ..............5-4 Decrement and Increment Instructions ............5-4 Compare and Test Instructions ................ 5-5 Boolean Logic Instructions ................5-6 5.10 Clear, Complement, and Negate Instructions ..........5-6 CPU12 MOTOROLA REFERENCE MANUAL...
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Software Interrupt Instruction ................7-6 Exception Processing Flow ................7-6 SECTION 8 DEVELOPMENT AND DEBUG SUPPORT External Reconstruction of the Queue ............. 8-1 Instruction Queue Status Signals..............8-1 Implementing Queue Reconstruction............... 8-3 Background Debug Mode ................8-6 Instruction Tagging..................8-13 MOTOROLA CPU12 REFERENCE MANUAL...
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CPU12 Design Goals ..................B-1 Source Code Compatibility................B-1 Programmer’s Model and Stacking ..............B-3 True 16-Bit Architecture ...................B-3 Improved Indexing....................B-6 Improved Performance..................B-9 Additional Functions..................B-11 APPENDIX C HIGH-LEVEL LANGUAGE SUPPORT Data Types...................... C-1 Parameters and Variables................C-1 Increment and Decrement Operators.............. C-3 CPU12 MOTOROLA REFERENCE MANUAL...
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Page Higher Math Functions ..................C-3 Conditional If Constructs ................. C-4 Case and Switch Statements ................C-4 Pointers ......................C-4 Function Calls ....................C-4 Instruction Set Orthogonality................C-5 APPENDIX D ASSEMBLY LISTING INDEX SUMMARY OF CHANGES MOTOROLA CPU12 REFERENCE MANUAL...
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Abnormal Membership Function Case 2............9-13 Abnormal Membership Function Case 3............9-13 REV Instruction Flow Diagram ............... 9-16 9-10 REVW Instruction Flow Diagram..............9-21 9-11 WAV and wavr Instruction Flow Diagram............9-25 9-12 Endpoint Table Handling................9-28 CPU12 MOTOROLA REFERENCE MANUAL...
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LIST OF TABLES Transfer and Exchange Postbyte Encoding...........A-24 Loop Primitive Postbyte Encoding (lb) ............A-25 Translated M68HC11 Mnemonics..............B-2 Instructions with Smaller Object Code .............B-3 Comparison of Math Instruction Speeds ............B-10 New M68HC12 Instructions ................B-11 MOTOROLA CPU12 REFERENCE MANUAL...
An instruction queue buffers program information so the CPU has immediate access to at least three bytes of machine code at the start of every instruction. In addition to the addressing modes found in other Motorola MCUs, the CPU12 offers an extensive set of indexed addressing capabilities including: •...
PPAGE — Program overlay page (bank) number for extended memory (>64K). Page — Program overlay page — High-order byte — Low-order byte ( ) — Content of register or memory location $ — Hexadecimal value % — Binary value MOTOROLA INTRODUCTION CPU12 REFERENCE MANUAL...
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A specific mnemonic within a range is referred to by mnemonic and number. A7 is bit 7 of accumulator A. A range of mnemonics is referred to by mnemonic and the numbers that define the range. DATA[15:8] form the high byte of the data bus. CPU12 INTRODUCTION MOTOROLA REFERENCE MANUAL...
PROGRAM COUNTER S X H I Z V C CONDITION CODE REGISTER HC12 PROG MODEL Figure 2-1 Programming Model 2.1.1 Accumulators General-purpose 8-bit accumulators A and B are used to hold operands and results of operations. Some instructions treat the combination of these two 8-bit accumulators (A : B) as a 16-bit double accumulator (D).
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M68HC11. 2.1.4 Program Counter The program counter (PC) is a 16-bit register that holds the address of the next instruc- tion to be executed. It is automatically incremented each time an instruction is fetched. MOTOROLA OVERVIEW CPU12 REFERENCE MANUAL...
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I bit are automatically set to prevent other interrupts from being recognized during the interrupt service routine. The mask bits are set after the registers are stacked, but before the interrupt vector is fetched. CPU12 OVERVIEW MOTOROLA REFERENCE MANUAL...
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The INX, DEX, INY, and DEY instructions affect the Z bit and no other condition flags. These operations can only determine = and ≠. 2.1.5.7 V Status Bit The V bit is set when two’s complement overflow occurs as a result of an operation. MOTOROLA OVERVIEW CPU12 REFERENCE MANUAL...
CPU executes more than one instruction at the same time, while the CPU12 always finishes execut- ing an instruction before beginning to execute another. Refer to SECTION 4 IN- STRUCTION QUEUE for more information. CPU12 OVERVIEW MOTOROLA REFERENCE MANUAL...
16-bit constant offset from x, y, sp, or pc (16-bit offset) (16-bit offset in two extension bytes) Indexed-Indirect Pointer to operand is found at... (D accumulator INST [D, xysp ] [D,IDX] x, y, sp, or pc plus the value in D offset) CPU12 ADDRESSING MODES MOTOROLA REFERENCE MANUAL...
16-bit immediate value but only an 8-bit value is supplied. In this case the assembler will generate the 16-bit value $0067 because the CPU ex- pects a 16-bit value in the instruction stream. BRSET FOO,#$03,THERE MOTOROLA ADDRESSING MODES CPU12 REFERENCE MANUAL...
This addressing mode can be used to access any lo- cation in the 64-Kbyte memory map. Example: LDAA $F03B This is a very basic example of extended addressing. The value from address $F03B is loaded into the A accumulator. CPU12 ADDRESSING MODES MOTOROLA REFERENCE MANUAL...
$FC with a BRCLR that accesses memory using an 8-bit indexed postbyte sets up a loop that executes until all the bits in the specified memory byte that corre- spond to ones in the mask byte are cleared. MOTOROLA ADDRESSING MODES CPU12...
A special group of instructions (LEAS, LEAX, and LEAY) cause this calculated effective address to be loaded into an index register for further calculations. CPU12 ADDRESSING MODES MOTOROLA REFERENCE MANUAL...
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In the first example, A will be loaded with the value from address $1000. In the second example, the value from the B accumulator will be stored at address $1FF8 ($2000 – $8). MOTOROLA ADDRESSING MODES CPU12 REFERENCE MANUAL...
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The square brackets distinguish this addressing mode from 16-bit constant offset indexing. Example: LDAA [10,X] CPU12 ADDRESSING MODES MOTOROLA REFERENCE MANUAL...
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M68HC11 stack, PSHA is equivalent to STAA 1,SP– and PULA is equivalent to LDAA 1,+SP. However, in the M68HC11, 16-bit operations like PSHX and PULX require mul- tiple instructions to decrement the SP by one, then store X, then decrement SP by one again. MOTOROLA ADDRESSING MODES CPU12 REFERENCE MANUAL...
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The square brackets distinguish this ad- dressing mode from D accumulator offset indexing. Example: [D,PC] DC.W PLACE1 DC.W PLACE2 DC.W PLACE3 CPU12 ADDRESSING MODES MOTOROLA REFERENCE MANUAL...
PC-relative indexing with move instructions by providing for PC offsets in source code. Table 3-3 shows PC offsets from the location immediately following the current in- struction by addressing mode. MOTOROLA ADDRESSING MODES CPU12 3-10 REFERENCE MANUAL...
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$18 is the page pre-byte, 09 is the MOVB opcode for ext-idx, C2 is the indexed post- byte for 2,PC (without correction). The Motorola MCUasm assembler produces corrected object code for PC-relative moves (18 09 C0 20 00 for the example shown). Note that, instead of assembling the 2,PC as C2, the correction has been applied to make it C0.
The RTC instruction restores the saved program page value and the return address from the stack. This causes execution to resume at the next instruction after the orig- inal CALL instruction. Refer to SECTION 10 MEMORY EXPANSION for a detailed discussion of memory ex- pansion. MOTOROLA ADDRESSING MODES CPU12 3-12 REFERENCE MANUAL...
Two external pins, IPIPE[1:0], provide time-multiplexed information about data move- ment in the queue and instruction execution. Decoding and use of these signals is dis- cussed in SECTION 8 DEVELOPMENT AND DEBUG SUPPORT. CPU12 INSTRUCTION QUEUE MOTOROLA REFERENCE MANUAL...
The following information is provided to enhance subsequent descriptions of instruction execution. MOTOROLA INSTRUCTION QUEUE CPU12 REFERENCE MANUAL...
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CALL and RTC execute correctly in the normal 64-Kbyte address space, thus provid- ing for portable code. However, since extra execution cycles are required, routinely substituting CALL/RTC for JSR/RTS is not recommended. CPU12 INSTRUCTION QUEUE MOTOROLA REFERENCE MANUAL...
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In all other cases, the op- tional cycle appears as a free cycle. MOTOROLA INSTRUCTION QUEUE CPU12...
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If the queue is not yet ready to advance, the third word of program information is held in the buffer. CPU12 INSTRUCTION QUEUE MOTOROLA REFERENCE MANUAL...
Store instructions automatically update the N and Z condition code bits, which can eliminate the need for a separate test in- struction in some programs. Table 5-1 is a summary of load and store instructions. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL...
All the bits in the upper byte of the 16-bit result are given the value of the MSB of the 8-bit number. SECTION 6 INSTRUCTION GLOSSARY contains information concerning other transfers and exchanges between 8- and 16-bit registers. Table 5-2 is a summary of transfer and exchange instructions. MOTOROLA INSTRUCTION SET OVERVIEW CPU12 REFERENCE MANUAL...
Signed and unsigned 8- and 16-bit subtraction can be performed between registers or between registers and memory. Special instructions support index calculation. Instruc- tions that subtract the CCR carry bit facilitate multiple precision computation. Refer to Table 5-4 for addition and subtraction instructions. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL...
CCR, they are particularly well suited for loop counters in multiple-precision computation routines. Refer to 5.19 Loop Primitive Instructions for information con- cerning automatic counter branches. Table 5-6 is a summary of decrement and incre- ment instructions. MOTOROLA INSTRUCTION SET OVERVIEW CPU12 REFERENCE MANUAL...
Test Instructions Mnemonic Function Operation Test Memory for Zero or Minus (M) – $00 TSTA Test A for Zero or Minus (A) – $00 TSTB Test B for Zero or Minus (B) – $00 CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL...
Two’s Complement Memory $00 – (A) ⇒ A or (A) + 1 ⇒ A NEGA Two’s Complement A $00 – (B) ⇒ B or (B) + 1 ⇒ B NEGB Two’s Complement B MOTOROLA INSTRUCTION SET OVERVIEW CPU12 REFERENCE MANUAL...
(M) • (mm) ⇒ M BCLR Clear Bits in Memory (A) • (M) BITA Bit Test A (B) • (M) BITB Bit Test B (M) + (mm) ⇒ M BSET Set Bits in Memory CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL...
Rotate Left Memory Through Carry ROLA Rotate Left A Through Carry ROLB Rotate Left B Through Carry Rotate Right Memory Through Carry RORA Rotate Right A Through Carry RORB Rotate Right B Through Carry MOTOROLA INSTRUCTION SET OVERVIEW CPU12 REFERENCE MANUAL...
Because WAV requires a number of cycles to execute, it can be interrupted. The wavr pseudo-instruction causes execution to resume at the point it was interrupted. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL...
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Weighted Average Calculation Results Are Placed in Correct Registers ∑ ⇒ For EDIV immediately After WAV Resumes Execution of Recover immediate results from stack wavr Interrupted WAV Instruction rather than initializing them to zero. MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-10 REFERENCE MANUAL...
8- to 16-bit multiply and accumulate operation that obtains a numerator for the weighted average calculation. The EMACS instruction can auto- mate this portion of the averaging operation when 16-bit operands are used. Table 5- shows the EMACS instruction. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-11...
8-Bit Table Lookup and Interpolate Initialize B, and index before TBL. (no indirect addressing modes allowed.) <ea> points to the first 8-bit table entry (M) B is fractional part of lookup value. MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-12 REFERENCE MANUAL...
This permits branching from any location in the standard 64-Kbyte address map to any other loca- tion in the map. Table 5-18 is a summary of the long branch instructions. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-13...
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Branch if Greater Than R ≤ M Z + (N ⊕ V) = 1 Branch if Less Than or Equal R < M N ⊕ V = 1 Branch if Less Than MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-14 REFERENCE MANUAL...
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Long Branch if Greater Than V) = 0 ⊕ Z + (N LBLE Long Branch if Less Than or Equal V) = 1 ⊕ LBLT Long Branch if Less Than V = 1 CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-15...
Test counter and branch if ≠ 0 If (counter) not = 0, then branch TBNE (counter = A, B, D, X,Y, or SP) else continue to next instruction MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-16 REFERENCE MANUAL...
(A, B, CCR, D, X, Y, or SP) ⇔ (A, B, CCR, D, X, Y, or SP) Exchange Register to Register (D) ⇔ (X) XGDX EXchange D with X (D) ⇔ (Y) XGDY EXchange D with Y CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-19...
8-bit accumulators A and B or 16-bit accumulator D to be added to the contents of the X and Y index registers, the SP, or the PC. Table 5-25 is a summary of pointer and index instructions. MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-20 REFERENCE MANUAL...
The wait instruction (WAI) stacks a return address and the contents of CPU registers and accumulators, then waits for an interrupt service request; however, system clock signals continue to run. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-21...
Mnemonic Function Operation If BDM enabled, enter BDM; BGND Enter Background Debug Mode else, resume normal processing Branch Never Does not branch LBRN Long Branch Never Does not branch Null operation — MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-22 REFERENCE MANUAL...
Address Mode Obje #opr16i CE jj opr8a DE d opr16a FE h oprx0_xysp ID X DETAILED SYNTAX oprx9,xysp IDX1 oprx16,xysp IDX2 CYCLE-BY-CYCLE [D,xysp] [D,IDX] OPERATION [oprx16,xysp] [IDX2] EX GLO PG Figure 6-1 Example Glossary Page CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL...
— Signed relative offset $80 (–128) to $7F (+127). Offset relative to the byte following the relative offset byte, or low-order byte of a 16-bit relative offset for long branches. xb — Indexed addressing post-byte. MOTOROLA INSTRUCTION GLOSSARY CPU12 REFERENCE MANUAL...
D, index registers X or Y, or the SP. Some assemblers may accept t2, T2, t3, or T3 codes in certain cases of transfer and exchange instructions, but these forms are intended for Motorola use only. abd — Any one legal register designator for accumulators A or B or the double accumu- lator D.
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— Any one legal register designation for index registers X or Y, the SP, or the PC. The reference point for PC relative instructions is the next address after the last byte of object code for the current instruction. MOTOROLA INSTRUCTION GLOSSARY CPU12...
— Write 8-bit PPAGE register. These cycles are only used with the CALL and RTC instructions to write the destination value of the PPAGE register and are not vis- ible on the external bus. Since the PPAGE register is an internal 8-bit register, these cycles are never stretched. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL...
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— Unstack 8-bit data. These cycles are stretched only when controlled by a chip- select circuit programmed for slow memory. MOTOROLA INSTRUCTION GLOSSARY CPU12 REFERENCE MANUAL...
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The taken case requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU performs three program word fetch- es from that address. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL...
A7 • B7 + B7 • R7 + R7 • A7 Set if there was a carry from the MSB of the result; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 06 MOTOROLA INSTRUCTION GLOSSARY CPU12 REFERENCE MANUAL...
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Address Mode Object Code Cycles Access Detail ABX translates to... 1A E5 LEAX B,X Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL...
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Object Code Cycles Access Detail ABY translates to... 19 ED LEAY B,Y Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-10 REFERENCE MANUAL...
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Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ANDCC # opr8i 10 ii MOTOROLA INSTRUCTION GLOSSARY CPU12 6-18 REFERENCE MANUAL...
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ASL oprx9,xysp IDX1 68 xb ff rPOw ASL oprx16,xysp IDX2 68 xb ee ff frPPw ASL [D ,xysp ] [D,IDX] 68 xb fIfrPw ASL [ oprx16,xysp ] [IDX2] 68 xb ee ff fIPrPw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-19...
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(for values of N and C after the shift). Set if the MSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ASLA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-20 REFERENCE MANUAL...
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(for values of N and C after the shift). Set if the MSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ASLB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-21...
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(for values of N and C after the shift). Set if the MSB of D was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ASLD MOTOROLA INSTRUCTION GLOSSARY CPU12 6-22 REFERENCE MANUAL...
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ASR oprx9,xysp IDX1 67 xb ff rPOw ASR oprx16,xysp IDX2 67 xb ee ff frPPw ASR [D ,xysp ] [D,IDX] 67 xb fIfrPw ASR [ oprx16,xysp ] [IDX2] 67 xb ee ff fIPrPw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-23...
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(for values of N and C after the shift). Set if the LSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ASRA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-24 REFERENCE MANUAL...
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(for values of N and C after the shift). Set if the LSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ASRB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-25...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-26 REFERENCE MANUAL...
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BCLR oprx9,xysp, msk8 IDX1 0D xb ff mm rPwP BCLR oprx16,xysp, msk8 IDX2 0D xb ee ff mm frPwOP Notes: 1. Indirect forms of indexed addressing cannot be used with this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-27...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-28 REFERENCE MANUAL...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-29...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-30 REFERENCE MANUAL...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-32 REFERENCE MANUAL...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-33...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-34 REFERENCE MANUAL...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-37...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-38 REFERENCE MANUAL...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-39...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-40 REFERENCE MANUAL...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-41...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-42 REFERENCE MANUAL...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-43...
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0F xb ff mm rr BRCLR oprx9,xysp, msk8, rel8 IDX1 rffPPP 0F xb ee ff mm BRCLR oprx16,xysp, msk8, rel8 IDX2 frPffPPP Notes: 1. Indirect forms of indexed addressing cannot be used with this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-45...
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0E xb ff mm rr BRSET oprx9,xysp, msk8, rel8 IDX1 rffPPP 0E xb ee ff mm BRSET oprx16,xysp, msk8, rel8 IDX2 frPffPPP Notes: 1. Indirect forms of indexed addressing cannot be used with this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-47...
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BSET oprx9,xysp, msk8 IDX1 0C xb ff mm rPwP BSET oprx16,xysp, msk8 IDX2 0C xb ee ff mm frPwOP Notes: 1. Indirect forms of indexed addressing cannot be used with this instruction. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-48 REFERENCE MANUAL...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-50 REFERENCE MANUAL...
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C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-51...
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A7 • B7 + B7 • R7 + R7 + A7 Set if there was a borrow from the MSB of the result; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 17 CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-53...
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IDX1 61 xb ff rPOw COM oprx16 xysp IDX2 61 xb ee ff frPPw xysp ] COM [D [D,IDX] 61 xb fIfrPw COM [ oprx16 xysp ] [IDX2] 61 xb ee ff fIPrPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-62 REFERENCE MANUAL...
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Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. 1; Set (for M6800 compatibility). Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail COMA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-63...
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Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. 1; Set (for M6800 compatibility). Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail COMB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-64 REFERENCE MANUAL...
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AC xb CPD oprx9,xysp IDX1 AC xb ff CPD oprx16,xysp IDX2 AC xb ee ff fRPP CPD [D ,xysp ] [D,IDX] AC xb fIfRfP CPD [ oprx16,xysp ] [IDX2] AC xb ee ff fIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-65...
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AF xb CPS oprx9,xysp IDX1 AF xb ff CPS oprx16,xysp IDX2 AF xb ee ff fRPP CPS [D ,xysp ] [D,IDX] AF xb fIfRfP CPS [ oprx16,xysp ] [IDX2] AF xb ee ff fIPRfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-66 REFERENCE MANUAL...
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AD xb CPY oprx9,xysp IDX1 AD xb ff CPY oprx16,xysp IDX2 AD xb ee ff fRPP CPY [D ,xysp ] [D,IDX] AD xb fIfRfP CPY [ oprx16,xysp ] [IDX2] AD xb ee ff fIPRfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-68 REFERENCE MANUAL...
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Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. Undefined. Represents BCD carry. See table above. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 07 CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-69...
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DEC oprx9,xysp IDX1 63 xb ff rPOw DEC oprx16,xysp IDX2 63 xb ee ff frPPw DEC [D ,xysp ] [D,IDX] 63 xb fIfrPw DEC [ oprx16,xysp ] [IDX2] 63 xb ee ff fIPrPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-72 REFERENCE MANUAL...
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Two’s complement overflow occurs if and only if (A) was $80 before the operation. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail DECA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-73...
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Two’s complement overflow occurs if and only if (B) was $80 before the operation. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail DECB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-74 REFERENCE MANUAL...
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Object Code Cycles Access Detail DES translates to... 1B 9F LEAS –1,SP Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-75...
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Condition Codes and Boolean Formulas: ∆ – – – – – – – Set if result is $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail MOTOROLA INSTRUCTION GLOSSARY CPU12 6-76 REFERENCE MANUAL...
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Condition Codes and Boolean Formulas: ∆ – – – – – – – Set if result is $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-77...
Page 138
Set if the result was > $FFFF; cleared otherwise. Undefined after di- vision by zero. Set if divisor was $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail EDIV ffffffffffO MOTOROLA INSTRUCTION GLOSSARY CPU12 6-78 REFERENCE MANUAL...
Page 139
Set if divisor was $0000; cleared otherwise. (Indicates division by zero.) Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail EDIVS 18 14 OffffffffffO CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-79...
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Source Form Address Mode Object Code Cycles Access Detail EMACS opr16a Special 18 12 hh ll ORROfffRRfWWP Notes: 1. opr16a is an extended address specification. Both X and Y point to source operands. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-80 REFERENCE MANUAL...
Page 145
Set if result is $00000000; cleared otherwise. Set if bit 15 of the result is set; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail EMUL CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-85...
Page 146
Set if result is $00000000; cleared otherwise. Set if bit 15 of the result is set; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail EMULS 18 13 MOTOROLA INSTRUCTION GLOSSARY CPU12 6-86 REFERENCE MANUAL...
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Set if MSB of result is set; cleared otherwise. Set if result is $0000; cleared otherwise. Undefined. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ETBL oprx0_xysp 18 3F xb ORRffffffP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-89...
Page 150
16-bit registers differ- ently. Exchanges of D with A or B are ambiguous. Cases involving TMP2 and TMP3 are reserved for Motorola use, so some assemblers may not permit their use, but it is possible to generate these cases by using DC.B or DC.W assembler directives.
Page 157
Two’s complement overflow occurs if and only if (A) was $7F before the operation. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail INCA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-97...
Page 158
Two’s complement overflow occurs if and only if (B) was $7F before the operation. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail INCB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-98 REFERENCE MANUAL...
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Object Code Cycles Access Detail INS translates to... 1B 81 LEAS 1,SP Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-99...
Page 160
Condition Codes and Boolean Formulas: ∆ – – – – – – – Set if result is $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail MOTOROLA INSTRUCTION GLOSSARY CPU12 6-100 REFERENCE MANUAL...
Page 161
Condition Codes and Boolean Formulas: ∆ – – – – – – – Set if result is $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-101...
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EF xb LDS oprx9,xysp IDX1 EF xb ff LDS oprx16,xysp IDX2 EF xb ee ff fRPP LDS [D ,xysp ] [D,IDX] EF xb fIfRfP LDS [ oprx16,xysp ] [IDX2] EF xb ee ff fIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-125...
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EE xb LDX oprx9,xysp IDX1 EE xb ff LDX oprx16,xysp IDX2 EE xb ee ff fRPP LDX [D ,xysp ] [D,IDX] EE xb fIfRfP LDX [ oprx16,xysp ] [IDX2] EE xb ee ff fIPRfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-126 REFERENCE MANUAL...
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ED xb LDY oprx9,xysp IDX1 ED xb ff LDY oprx16,xysp IDX2 ED xb ee ff fRPP LDY [D ,xysp ] [D,IDX] ED xb fIfRfP LDY [ oprx16,xysp ] [IDX2] ED xb ee ff fIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-127...
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LEAS oprx9,xysp IDX1 1B xb ff LEAS oprx16,xysp IDX2 1B xb ee ff Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-128 REFERENCE MANUAL...
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LEAX oprx9,xysp IDX1 1A xb ff LEAX oprx16,xysp IDX2 1A xb ee ff Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-129...
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LEAY oprx9,xysp IDX1 19 xb ff LEAY oprx16,xysp IDX2 19 xb ee ff Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-130 REFERENCE MANUAL...
Page 192
(for values of N and C after the shift). Set if the LSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSLA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-132 REFERENCE MANUAL...
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(for values of N and C after the shift). Set if the LSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSLB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-133...
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(for values of N and C after the shift). Set if the MSB of D was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSLD MOTOROLA INSTRUCTION GLOSSARY CPU12 6-134 REFERENCE MANUAL...
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(for values of N and C after the shift). Set if the LSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSRA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-136 REFERENCE MANUAL...
Page 197
(for values of N and C after the shift). Set if the LSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSRB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-137...
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Set if, after the shift operation, C is set; cleared otherwise. Set if the LSB of D was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSRD MOTOROLA INSTRUCTION GLOSSARY CPU12 6-138 REFERENCE MANUAL...
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– – – H, N, Z, V, and C may be altered by this instruction. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail Special RRfOw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-141...
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18 19 xb ff OrPO MINA oprx16,xysp IDX2 18 19 xb ee ff OfrPP MINA [D ,xysp ] [D,IDX] 18 19 xb OfIfrfP MINA [ oprx16,xysp ] [IDX2] 18 19 xb ee ff OfIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-142 REFERENCE MANUAL...
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MOVB oprx0_xysp, opr16a IDX–EXT 18 0D xb hh ll OrPwP MOVB oprx0_xysp, oprx0_xysp IDX–IDX 18 0A xb xb OrPwO Notes: 1. The first operand in the source code statement specifies the source for the move. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-144 REFERENCE MANUAL...
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MOVW oprx0_xysp, opr16a IDX–EXT 18 05 xb hh ll ORPWP MOVW oprx0_xysp, oprx0_xysp IDX–IDX 18 02 xb xb ORPWO Notes: 1. The first operand in the source code statement specifies the source for the move. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-145...
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– – – Set if bit 7 of the result (B bit 7) is set; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail MOTOROLA INSTRUCTION GLOSSARY CPU12 6-146 REFERENCE MANUAL...
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Set if there is a borrow in the implied subtraction from zero; cleared oth- erwise. Set in all cases except when (A) = $00. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail NEGA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-148 REFERENCE MANUAL...
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Set if there is a borrow in the implied subtraction from zero; cleared oth- erwise. Set in all cases except when (B) = $00. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail NEGB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-149...
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AA xb ORAA oprx9,xysp IDX1 AA xb ff ORAA oprx16,xysp IDX2 AA xb ee ff frPP ORAA [D ,xysp ] [D,IDX] AA xb fIfrfP ORAA [ oprx16,xysp ] [IDX2] AA xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-151...
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ORAB oprx9 , xysp IDX1 EA xb ff ORAB oprx16 , xysp IDX2 EA xb ee ff frPP ORAB [D ,xysp ] [D,IDX] EA xb fIfrfP ORAB [ oprx16,xysp ] [IDX2] EA xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-152 REFERENCE MANUAL...
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The X interrupt mask cannot be set by any software instruction. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ORCC # opr8i 14 ii CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-153...
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X bit set, leave it cleared, or change it from one to zero, but it can only be set by a reset or by recognition of an XIRQ interrupt. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PULC MOTOROLA INSTRUCTION GLOSSARY CPU12 6-162 REFERENCE MANUAL...
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$FF separator at the end of the rule list. Index register Y points to the base address for the fuzzy inputs and fuzzy outputs. The value in Y does not change during execution. MOTOROLA INSTRUCTION GLOSSARY CPU12...
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1. The 3-cycle loop in parentheses is executed once for each element in the rule list. When an interrupt occurs, there is a 2-cycle exit sequence, a 4-cycle re-entry sequence, then execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the interrupt. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-167...
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When execution is complete, Y points to the last weighting factor used. When weighting is not used (C = 0), Y is not changed. MOTOROLA INSTRUCTION GLOSSARY CPU12...
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When an interrupt occurs, there is a 2-cycle exit sequence, a 4- cycle re-entry sequence, then execution resumes with a prefetch of the last antecedent or consequent being pro- cessed at the time of the interrupt. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-169...
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ROL oprx9,xysp IDX1 65 xb ff rPOw ROL oprx16,xysp IDX2 65 xb ee ff frPPw ROL [D ,xysp ] [D,IDX] 65 xb fIfrPw ROL [ oprx16,xysp ] [IDX2] 65 xb ee ff fIPrPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-170 REFERENCE MANUAL...
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(for values of N and C after the shift). Set if the MSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ROLA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-171...
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(for values of N and C after the shift). Set if the MSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ROLB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-172 REFERENCE MANUAL...
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(for values of N and C after the shift). Set if the LSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail RORA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-174 REFERENCE MANUAL...
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(for values of N and C after the shift). Set if the LSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail RORB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-175...
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Set if the absolute value of B is larger than the absolute value of A; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 16 CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-179...
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SEX B,X SEX CCR,X sex:A ⇒ Y sex:B ⇒ Y sex:CCR ⇒ Y SEX A,Y SEX B,Y SEX CCR,Y sex:A ⇒ SP sex:B ⇒ SP sex:CCR ⇒ SP SEX A,SP SEX B,SP SEX CCR,SP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-185...
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6A xb STAA oprx9,xysp IDX1 6A xb ff STAA oprx16,xysp IDX2 6A xb ee ff STAA [D ,xysp ] [D,IDX] 6A xb PIfPw STAA [ oprx16,xysp ] [IDX2] 6A xb ee ff PIPPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-186 REFERENCE MANUAL...
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Object Code Cycles Access Detail VSPSSPSsP Notes: 1. The CPU also uses the SWI processing sequence for hardware interrupts and unimplemented opcode traps. A variation of the sequence (VfPPP) is used for resets. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-196 REFERENCE MANUAL...
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Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 0E CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-197...
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Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 0F CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-199...
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Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. Undefined. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TBL oprx0_xysp 18 3D xb OrrffffP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-201...
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The order in which transfers between 8-bit and 16- bit registers are specified affects the high byte of the 16-bit registers dif- ferently. Cases involving TMP2 and TMP3 are reserved for Motorola use, so some assemblers may not permit their use. It is possible to gen- erate these cases by using DC.B or DC.W assembler directives.
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Object Code Cycles Access Detail TRAP trapnum $18 tn OfVSPSSPSsP Notes: 1. The value tn represents an unimplemented page 2 opcode in either of the two ranges $30 to $39 or $40 to $FF. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-205...
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Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TSTA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-207...
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Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TSTB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-208 REFERENCE MANUAL...
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I mask bit (and the X mask bit, if the interrupt was XIRQ) to be set as the interrupt vector is fetched. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail WAI (before interrupt) OSSSfSsf (when interrupt comes) VfPPP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-213...
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Object Code Cycles Access Detail Special See note 18 3C Off(frrfffff)O (add if interrupted) SSSUUUrr Notes: 1. The 8-cycle sequence in parentheses represents the loop for one iteration of SOP and SOW accumulation. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-214 REFERENCE MANUAL...
The CPU12 can handle up to 64 exception vectors, but the number actually used var- ies from device to device, and some vectors are reserved for Motorola use. Refer to device documentation for more information.
CPU12. The CPU fetches a vector determined by the type of reset that has occurred, jumps to the address pointed to by the vector, and begins to execute code at that address. MOTOROLA EXCEPTION PROCESSING CPU12...
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The higher the vector address, the higher the priority of the interrupt. Typically, a de- vice integration module incorporates logic that can give one maskable source priority over other maskable sources. CPU12 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL...
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At the end of the interrupt service routine, an RTI instruction restores context from the stacked registers, and normal program execution resumes. MOTOROLA EXCEPTION PROCESSING CPU12 REFERENCE MANUAL...
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This differs from the M68HC11 illegal opcode interrupt, which uses the ad- dress of an illegal opcode as the return address. In the CPU12, the stacked return ad- dress can be used to calculate the address of the unimplemented opcode for software- controlled traps. CPU12 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL...
Fetches start at the address pointed to by the reset vector. When the fetches are completed, exception processing ends, and the CPU starts ex- ecuting the instruction at the head of the instruction queue. MOTOROLA EXCEPTION PROCESSING CPU12...
Set I bit If XIRQ, set X bit 9.2 - P Fetch program word 9.1 - P Fetch program word Finish filling instruction queue Finish filling instruction queue CPU12EXPFLOW Figure 7-2 Exception Processing Flow Diagram CPU12 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL...
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Cycle 9.1/9.2 is the third of three program word fetches that refill the instruction queue. It is the last cycle of exception processing. After this cycle the CPU starts executing the first cycle of the instruction at the head of the instruction queue. MOTOROLA EXCEPTION PROCESSING CPU12...
During reset, the pins are used as mode-select input sig- nals MODA and MODB. After reset, information on the pins does not become valid un- til an instruction reaches queue stage 2. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL...
Advance queue and load from bus Advance queue and load from latch Execution Start Mnemonic Meaning (capture at E fall) — No start Start interrupt sequence Start even instruction Start odd instruction MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 REFERENCE MANUAL...
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2 of the opcode map as a special 1-byte, 1-cycle instruction, except that interrupts are not recognized at the boundary between the prebyte and the rest of the instruction. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL...
8.3.1.2 fetch_add, fetch_dat Registers These registers buffer address and data for information that was fetched before the queue was ready to advance. MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 REFERENCE MANUAL...
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However, the cycle to fetch the next word of program infor- mation has already started and the data is on its way. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL...
ENBDM is cleared by another debugging command. Second, BDM must be activated to map the ROM and BDM control registers to addresses $FF00 to $FFFF and put the MCU in back- ground mode. MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 REFERENCE MANUAL...
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Ten target E-cycles later, the target senses the bit level on the BKGD pin. The host can drive high during host-to-target transmission to speed up rising edges, because the target does not drive the pin during this time. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL...
R-C RISE BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN CPU12 BDM TH TIM 1 Figure 8-3 BDM Target to Host Serial Bit Timing (Logic 1) MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 REFERENCE MANUAL...
BACKGROUND, do not require the CPU to be in BDM mode for ex- ecution. The control logic uses CPU dead cycles to execute these instructions. If a dead cycle cannot be found within 128 cycles, the control logic steals cycles from the CPU. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL...
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CPU oper- ation. However, if an operation requires multiple cycles, CPU clocks are frozen until the operation is complete. MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 8-10...
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BDM firmware to execute commands. The registers can be accessed by means of the hardware READ_BD and WRITE_BD commands, but must not be written during BDM operation. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL 8-11...
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TRACE — Trace Flag Shows when tracing is enabled. NOTE Execute a TRACE1 command to enable instruction tagging. Do not attempt to write TRACE directly. 0 = Tracing not enabled 1 = Tracing active MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 8-12 REFERENCE MANUAL...
ECLK performs the indicated function. Tagging is allowed in all modes. Tagging is disabled when BDM becomes active. Table 8-5 Tag Pin Function TAGHI TAGLO No Tag Low Byte High Byte Both Bytes CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL 8-13...
SWI. When BDM is forced, the CPU executes a BGND instruction. However, because these operations are not part of the normal flow of instruction execution, the control program must keep track of the actual breakpoint address. MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12...
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Registers can be used to match the high and low bytes of addresses for single and dual breakpoints, to match data for single breakpoints, or to do both functions. Use of the registers is generally determined by control bit settings. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL 8-15...
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MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 8-16 REFERENCE MANUAL...
By incorporating fuzzy logic support into a high-volume, general-pur- pose microcontroller product family, Motorola has made fuzzy logic available for a huge base of applications. 9.2 Fuzzy Logic Basics This is an overview of basic fuzzy logic concepts.
Page 302
Choosing a periodic rate for a fuzzy control system is the same as it would be for a conventional control system. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
$40 is stored to a RAM location, and is called a fuzzy input (in this case, the fuzzy input for “temperature is warm”). There is a RAM location for each fuzzy input (for each label of each system input). CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL...
The end result of the fuzzification step is a table of fuzzy inputs representing current system conditions. MOTOROLA FUZZY LOGIC SUPPORT CPU12 REFERENCE MANUAL...
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There also must be a way to know when the last rule in the system has been reached. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL...
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One method of organization is to have a fixed number of rules with a specific number of antecedents and consequents. A second method, employed in Motorola Freeware M68HC11 kernels, is to mark the end of the rule list with a reserved value, and use a bit in the pointers to distinguish antecedents from consequents.
Lines 9 and 10 form a loop to fuzzify the seven labels of the second system input. When the program drops to line 11, the Y index register is pointing at the next location after the last fuzzy input, which is the first fuzzy output in this system. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL...
$FF character is found. For a system of 17 rules with two ante- cedents and one consequent each, the REV instruction takes 259 cycles, but it is in- terruptible so it does not cause a long interrupt latency. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
Typically, there are three to seven labels per system input, but there is no practical restriction on this number as far as the fuzzification step is concerned. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL...
CPU processes. It is common for several internal functions to take place during a single CPU cycle (for example, in cycle 2, two 8-bit subtractions take place and a flag is set based on the results). MOTOROLA FUZZY LOGIC SUPPORT CPU12...
$FF as far as the right sloping side is concerned. 4a decides if the value is left of the right sloping side (Grade = $FF), or on the sloping portion of the right side of the trapezoid (Grade = Grade_2). 4b could still override this tentative value in grade. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-11...
If point_1 was to the right of point_2, flag_d12n would force the result to be $00 for all input values. In fact, flag_d12n always limits the region of interest to the space greater than or equal to point_1 and less than or equal to point_2. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
One uses 8-bit offsets in the encoded rules, while the other uses full 16-bit addresses. This affects the size of the rule data structure and execution time. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-13...
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A is automatically set to $FF when the instruction detects the $FE marker character between the last consequent of the previous rule, and the first antecedent of a new rule. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
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(refer to SECTION 6 INSTRUCTION GLOSSA- for details). Lower case letters indicate a cycle where 8-bit or no data is transferred. Upper case letters indicate cycles where 16-bit or no data is transferred. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-15...
A = A (no change to A) = $FF (end of rules)? 7.0 - O Read program word if $3A misaligned REV INST FLOW Figure 9-9 REV Instruction Flow Diagram MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-16 REFERENCE MANUAL...
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During cycle 5.0, a new rule byte is read unless this is the last loop pass, and R $FF (marking the end of the rule list). This new rule byte will not be used until cycle 4.0 of the next pass through the loop. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-17...
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$FFFE, and the end of the last rule is marked by the reserved 16-bit value $FFFF. Since $FFFE and $FFFF correspond to the addresses of the reset vector, there would never be a fuzzy input or output at either of these locations. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
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(weighted) for the current rule. If the current truth value is larger, it is written over the previous value in the fuzzy output. After all rules have been evaluated, the fuzzy output contains the truth value for the most-true rule that referenced that fuzzy output. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-19...
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(refer to SECTION 6 IN- STRUCTION GLOSSARY for details). Lower case letters indicate a cycle where 8-bit or no data is transferred. Upper case letters indicate cycles where 16-bit data could be transferred. MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-20 REFERENCE MANUAL...
Adjust PC to point at next instruction 8.2 - f If C = 1 (weights enabled), Y = TMP2 + 1 Finish multiply REVW INST FLW Figure 9-10 REVW Instruction Flow Diagram CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-21...
The WAV instruction performs weighted average calculations used in defuzzification. The pseudo-instruction wavr is used to resume an interrupted weighted average op- eration. WAV calculates the numerator and denominator sums using: ∑ System Output --------------------- - ∑ MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-22 REFERENCE MANUAL...
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PC is ad- justed again as it was for the first interrupt. WAV can be interrupted any number of times, and additional WAV instructions can be executed while a WAV instruction is in- terrupted. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-23...
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2.1 through 6.1 plus 7.0 through 11.0 plus 4.0 through 6.0 plus the exit 7.1 through 9.1. This is a worst-case total of 17 cycles. MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-24...
12.0 - O Read program word if $3C misaligned Adjust PC to point at next instruction Y : D = TMP3 : TMP2; X = TMP1 WAV INST FLOW Figure 9-11 WAV and wavr Instruction Flow Diagram CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-25...
The excessive size to specify tabular member- ship functions makes them impractical for most microcontroller-based fuzzy systems. The CPU12 instruction set includes two instructions (TBL and ETBL) for lookup and interpolation of compressed tables. MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-26...
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The table is entered with the x-coordinate of the desired point to lookup in the A accumulator. When the table is exited, the corresponding y-value is in the A accumulator. Figure 9-12 shows one way to work with this type of table. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-27...
It makes intuitive sense that the exact shape of a membership function is much less important than the fact that it has gradual boundaries. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
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There are two main areas where other CPU12 instructions can help with custom de- fuzzification routines. The first case is working with operands that are more than eight bits. The second case involves using an entirely different approach than weighted av- erage of singletons. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-29...
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8-MHz cycles. The EMACS instruction uses 16-bit operands and accumulates the result in a 32-bit memory location, taking only twelve 8-MHz cycles per iteration, including accessing all operands from memory and storing the result to memory. MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-30...
EEPROM. The program window al- ways occupies the 16-Kbyte space from $8000 to $BFFF. Data and extra windows can vary in size and location. CPU12 MEMORY EXPANSION MOTOROLA REFERENCE MANUAL 10-1...
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$FF00 to $FF06. The BDM ROM replaces the reg- ular system vectors while BDM is active, but BDM resources are not in the memory map during normal execution of application programs. MOTOROLA MEMORY EXPANSION CPU12...
Since the return operation is implemented as a single uninterruptable CPU instruction, the RTC can be executed from anywhere in memory, including from a different page of extended memory in the overlay window. CPU12 MEMORY EXPANSION MOTOROLA REFERENCE MANUAL 10-3...
DPAGE holds the page select for the data overlay, and EPAGE holds the page select for the extra page. The CPU12 manipu- lates the PPAGE register directly, so it will always be eight bits or less in devices that MOTOROLA MEMORY EXPANSION CPU12...
Enables (1) or disables (0) the CSP0 chip select. The default is enabled. This allows CSP0 to be used to select an external memory that includes the reset vector and start- up initialization programs. CPU12 MEMORY EXPANSION MOTOROLA REFERENCE MANUAL 10-5...
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10.5.2 Data Expansion Chip Select Controls The data chip select (CSD) has four associated control bits. 10.5.2.1 CSDE Control Bit Enables (1) or disables (0) the CSD chip select. The default is disabled. MOTOROLA MEMORY EXPANSION CPU12 10-6 REFERENCE MANUAL...
10.6 System Notes The expansion overlay windows are specialized for specific application uses, but there are no restrictions on the use of these memory spaces. Motorola MCUs have a mem- ory-mapped architecture in which all memory resources are treated equally. Although it is possible to execute programs in paged external memory in the data and extra overlay areas, it is less convenient than using the program overlay area.
TBNE. The first digit of the instruction postbyte corresponds to the columns of the ta- ble. The second digit of the postbyte corresponds to the rows. The body of the table shows actions caused by the postbyte. CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL...
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C3 jj kk – – Add 16-Bit to D (A:B) D3 dd F3 hh ll E3 xb IDX1 E3 xb ff IDX2 E3 xb ee ff [D,IDX] E3 xb [IDX2] E3 xb ee ff MOTOROLA INSTRUCTION REFERENCE CPU12 REFERENCE MANUAL...
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0C xb ee ff mm (SP) – 2 ⇒ SP; BSR rel 07 rr – – – – – – – – ⇒ M :RTN (SP) (SP+1) Subroutine address ⇒ PC Branch to Subroutine MOTOROLA INSTRUCTION REFERENCE CPU12 REFERENCE MANUAL...
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(B) – (M) C1 ii – – Compare Accumulator B with Memory D1 dd F1 hh ll E1 xb IDX1 E1 xb ff IDX2 E1 xb ee ff [D,IDX] E1 xb [IDX2] E1 xb ee ff CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL...
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– – – – – – If (cntr) not = 0, then Branch; (9-bit) else Continue to next instruction Decrement Counter and Branch if ≠ 0 (cntr = A, B, D, X, Y, or SP) MOTOROLA INSTRUCTION REFERENCE CPU12 REFERENCE MANUAL...
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A = current crisp input value; X points at 4-byte data structure that de- scribes a trapezoidal membership function (P1, P2, S1, S2); Y points at fuzzy input (RAM location). See instruction details for special cases. CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-11...
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EA xb ee ff [D,IDX] EA xb [IDX2] EA xb ee ff M ⇒ CCR ⇑ ⇑ ⇑ ⇑ ⇑ ⇑ ⇑ ORCC opr (CCR) 14 ii – Logical OR CCR with Memory MOTOROLA INSTRUCTION REFERENCE CPU12 A-12 REFERENCE MANUAL...
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Y. Each rule output is an 8- bit offset from the base address in Y. $FE separates rule inputs from rule outputs. $FF terminates the rule list. REV may be interrupted. CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-13...
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– – – – – – (SP) (SP+1) (SP) + 2 ⇒ SP Return from Subroutine (A) – (B) ⇒ A – – ∆ ∆ ∆ ∆ 18 16 – – Subtract B from A MOTOROLA INSTRUCTION REFERENCE CPU12 A-14 REFERENCE MANUAL...
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C0 ii – – Subtract Memory from Accumulator B D0 dd F0 hh ll E0 xb IDX1 E0 xb ff IDX2 E0 xb ee ff [D,IDX] E0 xb [IDX2] E0 xb ee ff MOTOROLA INSTRUCTION REFERENCE CPU12 A-16 REFERENCE MANUAL...
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Transfer Register to Register r1 and r2 may be A, B, CCR, D, X, Y, or SP (CCR) ⇒ A B7 20 – – – – – – – – Translates to TFR CCR , A CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-17...
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X points at first element in S list. Y points at first element in F list. All S and F elements are 8-bits. If interrupted, six extra bytes of stack used for intermediate values MOTOROLA INSTRUCTION REFERENCE CPU12 A-18 REFERENCE MANUAL...
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IM — Immediate RL — Relative SP — Special Cycle counts are for single-chip mode with 16-bit internal buses. Stack location (internal or external), external bus width, and operand alignment can affect actual execution time. CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-19...
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10 = D (16-bit) 11 = see accumulator D offset indexed-indirect rr can specify X, Y, SP, or PC 111rr111 [D,r] Accumulator D offset indexed-indirect rr can specify X, Y, SP, or PC MOTOROLA INSTRUCTION REFERENCE CPU12 A-24 REFERENCE MANUAL...
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IBEQ IBEQ IBNE IBNE (–) (–) (–) (–) (–) (–) postbyte (hex) counter used _BEQ (–) sign of 9-bit relative branch offset branch condition (lower eight bits are an extension byte following postbyte) CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-25...
CPU12 instructions. This translation is performed by the assembler so there is no need to modify an old M68HC11 program in order to assemble it for the CPU12. In fact, the M68HC11 mnemonics can be used in new CPU12 programs. CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL...
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Kbyte M68HC11 assembly code program, was reassembled for the CPU12. The re- sulting object code is six bytes smaller than the M68HC11 code. It is fair to conclude that M68HC11 code can be reassembled with very little change in size. MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12...
1974. The M6800 was strictly an 8-bit machine, with 8-bit data buses and 8-bit instructions. As Motorola devices evolved from the M6800 to the M68HC11, a number of 16-bit instructions were added, but the data buses remained eight bits wide, so these instructions were performed as sequences of 8-bit opera- tions.
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If the queue is aligned at the start of an instruction with an odd byte count, the last byte of object code shares a queue word with the opcode of the next instruction. Since this word holds part of the next instruction, the queue cannot ad- MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12...
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$01F2. With the last-used CPU12 stack, if the SP = $01F0 when execution begins, the sequence is: load X from $01F0:01F1; SP = SP + 2; and the SP again ends up at $01F2. The second sequence requires one less stack pointer adjustment. CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL...
5-, 9-, or 16-bit signed off- sets. This approach eliminates the differences between X and Y register use and dra- matically enhances indexed addressing capabilities. MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12...
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(–32,768 to +32767) or unsigned (0 to 65,535) value. In 16- bit constant offset mode, the offset is supplied in two extension bytes after the opcode and postbyte. CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL...
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This reduces the loop execution time from 15 cycles to six cycles. This re- duction, combined with the 8-MHz bus speed of the M68HC12 family, can have signif- icant effects. MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12 REFERENCE MANUAL...
B.6.2 Fast Math The CPU12 has some of the fastest math ever designed into a Motorola general-pur- pose MCU. Much of the speed is due to a 20-bit ALU that can perform two smaller op- erations simultaneously.
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CPU12 assembly language programs written from scratch tend to be 30% smaller than equivalent programs written for the M68HC11. This figure has been indepen- dently qualified by Motorola programmers and an independent C compiler vendor. The major contributors to the reduction appear to be improved indexed addressing and the universal transfer/exchange instruction.
Increment and Branch if Equal to Zero (Looping Primitive) IBNE Relative Increment and Branch if Not Equal to Zero (Looping Primitive) Signed Integer Divide D/X ⇒ X(Q) and D(R) (Signed) IDIVS Inherent CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL B-11...
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Table Lookup and Interpolate (8-bit Entries) TBNE Relative Test Register and Branch if Not Equal to Zero (Looping Primitive) Inherent Transfer Register Contents to Another Register Special Weighted Average (Fuzzy Logic Support) MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12 B-12 REFERENCE MANUAL...
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B.7.4 Long Branches All of the branch instructions from the M68HC11 are also available with 16-bit offsets which allows them to reach any location in the 64-Kbyte address space. CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL B-13...
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A kernel written for the M68HC11 required about 250 bytes and executed in about 750 milliseconds. The CPU12 kernel uses about 50 bytes and executes in about 50 microseconds. MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12...
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LDX 5,SP+ loads X with the value on the bottom of the stack and deallocates five bytes from the stack in a single operation that takes only two bytes of object code. CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL B-15...
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CALL instruction, the destination page value is provided as immedi- ate data in the instruction object code. CALL and RTC execute correctly in the normal 64-Kbyte address space, thus providing for portable code. MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12...
HLL. Larger program ROM size require- ments translate into increased system costs. Motorola solicited the cooperation of third-party software developers to assure that the CPU12 instruction set would meet the needs of a more efficient generation of compil- ers.
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Next, the called subroutine establishes a new frame pointer by executing a TFR S,X. Space is allocated for local variables by executing an LEAS –n,S, where n is the num- ber of bytes needed for local variables. MOTOROLA HIGH-LEVEL LANGUAGE SUPPORT CPU12...
16-bit value (the size of an integer data type). The 16-bit C value would need to be sign-extended into the upper 16-bits of the 32-bit EDIVS numerator before the divide operation. CPU12 HIGH-LEVEL LANGUAGE SUPPORT MOTOROLA REFERENCE MANUAL...
Since the CALL instruction is uninterruptible, this eliminates the need to sep- arately mask off interrupts during the context switch. MOTOROLA HIGH-LEVEL LANGUAGE SUPPORT CPU12...
Greater regularity of the instruction makes it possible to implement compilers more efficiently, because operation is more consistent, and fewer special cases must be handled. CPU12 HIGH-LEVEL LANGUAGE SUPPORT MOTOROLA REFERENCE MANUAL...
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MOTOROLA HIGH-LEVEL LANGUAGE SUPPORT CPU12 REFERENCE MANUAL...
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5f -1,y d613 ac 81 1,sp d6ab af 90 -16,sp d615 ac 01 d6ad af 10 -16,x d617 ac 41 d6af af 50 -16,y d619 ac bf 1,sp- d6b1 af f1 ef -17,sp CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL...
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1,+sp d7d3 ae ee d747 ae 20 1,+x d7d5 9e 55 d749 ae 60 1,+y d7d7 9e 55 d74b ae a7 8,+sp d7d9 be 01 88 d74d ae 27 8,+x d7dc be 01 88 MOTOROLA ASSEMBLY LISTING CPU12 REFERENCE MANUAL...
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9-17 to 9-20, 9-22, 9-29 Word moves 6-145 Write PPAGE cycle 6-5 Write 16-bit data cycle 6-6 Write 8-bit data cycle 6-6 X mask bit 2-3, 6-90, 6-162, 6-177, 6-189, 6-198, 6-203, 6-213 XGDX instruction 6-215 XGDY instruction 6-216 MOTOROLA CPU12 REFERENCE MANUAL...
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Table B-3, last row (EMACS) math operation corrected and two occurrences of B-10 “per iteration” removed. B-13 Section B.7.2, first sentence, “six transfer instructions” is now “eight transfer instructions.” Minor grammatical and typographic corrections to improve consistency and presentation. General New index markers. CPU12 SUMMARY OF CHANGES MOTOROLA REFERENCE MANUAL...
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MOTOROLA SUMMARY OF CHANGES CPU12 REFERENCE MANUAL...
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Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.