Motorola CPU32 Reference Manual page 265

II
Table 6-1. Exception Vector Assignments
Vector Vector Offset Assignment
Number Dec Hex Space
0 0
000 SP Reset: Initial Stack Pointer
1 4 004 SP
Reset: Initial Program Counter
2 8
008 SD Bus Error
3 12 OOC SD
Address Error
4 16 010 SD Illegal Instruction
5 20 014 SD
Zero Division
6
24 018 SD CHK, CHK2 Instructions
7
28 01C SD TRAPcc, TRAPV Instructions
8 32 020 SD Privilege Violation
9
36 024 SD Trace
10 40 028 SD
Line 1010 Emulator
11 44 02C SD Line 1111 Emulator
12 48 030 SD Hardware Breakpoint
13 52 034 SD (Reserved, Coprocessor Protocol Violation)
14 56 038 SD
Format Error and Uninitialized Interrupt
15 60 03C SD Format Error and Uninitialized Interrupt
16-23
64 040
SD (Unassigned, Reserved)
92 05C
24 96 060 SD Spurious Interrupt
25 100 064 SD Level 1 Interrupt Autovector
26
104 068 SD Level 2 Interrupt Autovector
27 108 06C
SD
Level 3 Interrupt Autovector
28 112 070 SD Level 4 Interrupt Autovector
29 116 074 SD Level 5 Interrupt Autovector
30 120 078 SD Level 6 Interrupt Autovector
31 124 07C SD Level 7 Interrupt Autovector
32-47
128 080
SD Trap Instruction Vectors (0-15)
188 OBC
48-58
192 OCO
SD (Reserved, Coprocessor)
232 OE8
59-63
236 OEC
SD (Unassigned, Reserved)
252 OFC
64-255
256 100
SD User Defined Vectors (192)
1020 3FC
Each vector is assigned an 8-bit number. Vector numbers for some exceptions
are obtained from an external device; others are supplied by the processor.
The processor multiplies the vector number by four to calculate vector offset,
then adds the offset to the contents of the VBR. The sum is the memory address
of the vector.
MOTOROLA
6-2
EXCEPTION PROCESSING CPU32 REFERENCE MANUAL