Motorola CPU32 Reference Manual page 292

at the address pointed to by SP - 6 (SP value is the value before initial stacking
on the faulted frame).
The frame can have either four or six words, depending on the type of error.
Four word stack frames do not include the faulted instruction program counter
(the internal transfer count register is located at SP
+
$10 and the SSW is
located at SP
+
$12).
The fault address of a dynamically sized bus cycle is the address of the upper
byte, regardless of the byte that caused the error.
SP~
+$02
+$06
+$08
+$OC
+$10
+$14
+$16
15
o
STATUS REGISTER
RETURN PROGRAM COUNTER HIGH
RETURN PROGRAM COUNTER LOW
1
I
1
I
0
I
0
I
VECTOR OFFSET
FAULTED ADDRESS HIGH
FAULTED ADDRESS LOW
DBUFHIGH
DBUFLOW
CURRENT INSTRUCTION PROGRAM COUNTER HIGH
CURRENT INSTRUCTION PROGRAM COUNTER LOW
INTERNAL TRANSFER COUNT REGISTER
010
I
SPECIAL STATUS WORD
Figure 6-6. Format $C - BERR Stack for Prefetches and Operands
CPU32 REFERENCE MANUAL
EXCEPTION PROCESSING
MOTOROLA
6-29