Toshiba H1 Series Data Book page 650

(1) Read cycle (0 waits)
X1
t
CL
SDCLK
WAIT
A0~A23
CSn
R/
W
t
AR
RD
t
RRH
D0~D15
SRxxB
SRWR
Note1: The phase relation between X1 input signal and the other signals is undefined.
Note2: The above timing chart show an example of basic bus
pins timing can be adjusted by memory controller timing adjust function.
t
OSC
t
CYC
t
CH
t t
TK KT
t
AD
t
RK
t
t
t
SBA
92CZ26A-647
RR
RD
Data input
timing. The , R/ W ,
CSn RD
TMP92CZ26A
t
HA
t
HR
, , ,
WRxx SRxxB SRWR