Toshiba H1 Series Data Book page 502

bit Symbol
I2S1CTL
(1818H)
Read/Write
After reset
Transmission
Function
0: Stop
1: Start
bit Symbol
Read/Write
(1819H)
After reset
Source
clock
Function 0: f
1: f
bit Symbol
I2S1C
(181AH)
Read/Write
After reset
Function
(181BH)
Bit symbol
Read/Write
After reset
Function
I2S1BUF
bit Symbol
(1810H)
Read/Write
After reset
Read-modify-
Function
write
instructions
cannot be
bit Symbol
used.
Read/Write
After reset
Function
I2S1 Control Register
7 6
TXE1 *CNTE1
R/W R/W
0 0
Counter
control
0: Clear
1: Start
15 14 13
CLKS1
R/W
0
SYS
PLL
I2S1 Divider Value Setting Register
7 6
CK17 CK16 CK15
R/W R/W R/W
0 0
Divider value for CK signal (8-bit counter)
15 14
WS15
R/W
15 14 13 12 11
B115 B114 B113 B112 B111
31 30 29 28 27
B131 B130 B129 B128 B127
Figure 3.18.3 I
5 4 3
DIR1 BIT1
R/W R/W
0 0
Bit length
Transmission
start bit
0: MSB 0: 8 bits
1: LSB 1:16 bits
12 11
FSEL1 TEMP1
R/W R
0 1
Stereo
Transmission
/monaural
FIFO state
0: Stereo 0: Data
1: Monaural 1: No data
5 4 3
CK14 CK13
R/W R/W
0 0 0
13 12 11
WS14 WS13
R/W R/W
0 0 0
Divider value for WS signal (6-bit counter)
I2S1 Buffer Register
10 9 8 7 6
B110 B109 B108 B107 B106
W
Undefined
Transmission buffer register (FIFO)
26 25 24 23 22
B126 B125 B124 B123 B122
W
Undefined
Transmission buffer register (FIFO)
2
S Channel 1 Control Registers
92CZ26A-499
TMP92CZ26A
2 1
DTFMT11 DTFMT10 SYSCKE1
R/W R/W
0 0
Output format System
clock
2
0: Disable
00: I S 10: Right
1: Enable
01: Left 11: Reserved
10 9
WLVL1 EDGE1 CLKE1
R/W R/W
0 0
WS level Data output Clock
clock edge operation
0: Low left 0: Falling (after
1: High left 1: Rising transmis-
sion)
0: Enable
1: Disable
2 1
CK12 CK11 CK10
R/W R/W R/W
0 0
10 9
WS12 WS11 WS10
R/W R/W R/W
0 0
5 4 3 2 1
B105 B104 B103 B102 B101
21 20 19 18 17
B121 B120 B119 B118 B117
0
R/W
0
8
R/W
0
0
0
8
0
0
B100
16
B116