Toshiba H1 Series Data Book page 24

The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only),
(b) PLL-ON Mode (X1, X2, and PLL).
Figure 3.3.1 shows a transition figure.
The clock frequency input from the X1 and X2 pins is called fOSCH and the clock
frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by
SYSCR1<GEAR2:0> is called the system clock fSYS. And one cycle of fSYS is defined to
as one state.
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
Note 1: If you shift from PLL-ON mode to PLL-OFF mode, execute following setting in the same order.
(1) Change CPU clock (Set "0" to PLLCR0<FCSEL>)
(2) Stop PLL circuit (Set "0" to PLLCR1<PLLON>)
Note 2: It's prohibited to shift from PLL-ON mode to STOP mode directly.
You should set PLL-OFF mode once, and then shift to STOP mode.
The clock frequency input from the X1 and X2 pins is called f
called fs. The clock frequency selected by SYSCR1<GEAR2:0> is called the system clock f
to as one state.
Reset
(f
OSCH
instruction
interrupt
PLL-OFF mode
instruction
(f
OSCH
interrupt
(a) PLL-OFF mode transition figure
Reset
(f
OSCH
instruction
interrupt
PLL-OFF
instruction
(f
OSCH
interrupt
instruction
interrupt
PLL-ON mode
instruction
((12 or 16)×f
interrupt
(b) PLL-OFF , PLL-ON mode transition figure
Figure 3.3.1 System clock block diagram
OSCH
92CZ26A-21
/16)
release Reset
instruction
interrupt
/gear value)
/16)
release Reset
instruction
mode
interrupt
/gear value)
Instruction (Note)
/gear value)
OSCH
and the clock frequency input from the XT1 and XT2 pins is
SYS
TMP92CZ26A
STOP mode
(Stops all circuits)
STOP mode
(Stops all circuits)
. And one cycle of f is defined
SYS