Toshiba H1 Series Data Book page 229

SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
A10
RA
A15-A0
RA
D15-D0
tRCD=
1CLK
Bank
Active
2CLK
SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
A10
RA
A15-A0
RA
D15-D0
D(n)
tRCD=
1CLK
Bank
Active
3CLK 2CLK
CA (n) CA (n+2)
D (n) D (n+2)
tWR= tWR=
1CLK 1CLK
Write Write
Figure3.10.4 Single Write Cycle Timing
1CLK 1CLK
CA(n)
D(n+2) D(n+4)
Write
Figure3.10.5 Burst Write Cycle Timing
92CZ26A-226
2CLK
CA (n+4)
D (n+4)
tWR=
1CLK
Write
Burst Stop Cycle 2CLK
A10
CA(n) A15-0
D(n+6) D(end)
Burst
Stop
TMP92CZ26A