Control Registers - Toshiba H1 Series Data Book

3.10.1 Control Registers

The SDRAMC has the following control registers.
Bit symbol
SDACR
Read/Write
(0250H)
After reset
Read data
shift
function
0: Disable
Function
1: Enable
Bit symbol
SDCISR
Read/Write
(0251H)
After reset
Function
Bit symbol
SDRCR
Read/Write
(0252H)
After reset
Always
write "0"
Function
SDRAM Access Control Register
7 6 5
–
SRDS SMUXW1 SMUXW0
R/W
1 0 0
Always
Address multiplex type
write "0"
00: Type A (A9- )
01: Type B (A10- )
10: Type C (A11- )
11: Reserved
SDRAM Command Interval Setting Register
7 6 5
STMRD STWR
1 1
TMRD TWR
0: 1 CLK 0: 1 CLK
1: 2 CLK 1: 2 CLK
SDRAM Refresh Control Register
7 6 5
−
R/W
0
4 3
SPRE
0 0
Read/Write
commands
0: Without
auto pre-
charge
1: With auto
precharge
4 3
STRP STRCD
R/W
1 1
TRP TRCD
0: 1 CLK 0: 1 CLK
1: 2 CLK 1: 2 CLK
4 3
SSAE SRS2
1 0
Self Refresh interval
Refresh 000: 47 states
auto exit 001: 78 states
function
010: 156 states 110: 936 states
0:Disable 011: 312 states 111: 1248 states
1:Enable
92CZ26A-221
TMP92CZ26A
2 1
SMAC
R/W
SDRAM
controller
0: Disable
1: Enable
2 1 0
STRC2 STRC1 STRC0
1 0 0
TRC
000: 1 CLK 100: 5 CLK
001: 2 CLK 101: 6 CLK
010: 3 CLK 110: 7 CLK
011: 4 CLK 111: 8 CLK
2 1
SRS1 SRS0 SRC
R/W
0 0
Auto
100: 468 states Refresh
101: 624 states
0:Disable
1:Enable
0
0
0
0