Toshiba H1 Series Data Book page 330

(12) Timing generation
a. In UART Mode
Receiving
Mode
Interrupt timing
Framing error timing
Parity error timing
Overrun error timing
Note1: In 9-Bit and 8-Bit + Parity Modes, interrupts coincide with the ninth bit pulse.
Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be
transferred) to allow checking for a framing error.
Note2: The higher the transfer rate, the later than the middle receive interrupts and errors occur.
Transmitting
Mode
Interrupt timing
b. I/O interface
Transmission SCLK Output Mode
Interrupt
SCLK Input Mode
timing
Receiving SCLK Output Mode
Interrupt
timing
SCLK Input Mode
8-Bit + Parity
9-Bit
(Note)
Center of last bit Center of last bit
(bit 8) (parity bit)
Center of stop bit Center of stop bit
Center of last bit
―
(parity bit)
Center of last bit Center of last bit
(bit 8) (parity bit)
9-Bit 8-Bit + Parity
Just before stop bit is Just before stop bit is
transmitted transmitted
Immediately after last bit. (See Figure 3.14.13.)
Immediately after rise of last SCLK signal Rising Mode, or
immediately after fall in Falling Mode. (See Figure 3.14.14.)
Timing used to transfer received to data Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See Figure 3.14.15.)
Timing used to transfer received data to Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See Figure 3.14.16.)
92CZ26A-327
8-Bit, 7-Bit + Parity, 7-Bit
(Note)
Center of stop bit
Center of stop bit
Center of stop bit
Center of stop bit
8-Bit, 7-Bit + Parity, 7-Bit
Just before
transmitted
TMP92CZ26A
stop bit is