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Toshiba TX79 Series User Manual

Tx system risc symmetric 2-way superscalar 64-bit cpu
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TX System RISC
TX79 Family
TMPR7901
(Symmetric 2-way superscalar
64-bit CPU)

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Summary of Contents for Toshiba TX79 Series

  • Page 1 TX System RISC TX79 Family TMPR7901 (Symmetric 2-way superscalar 64-bit CPU)
  • Page 2 Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.

  • Page 3: Table Of Contents

    Table Of Contents TABLE OF CONTENTS CHAPTER 1. INTRODUCTION ......................1-1 ..........................1-1 VERVIEW ......................... 1-1 ERMINOLOGY 1.2.1 Abbreviations used....................... 1-1 1.2.2 Other Terminology....................... 1-3 .......................... 1-3 ONVENTIONS CHAPTER 2. FEATURES........................2-1 CHAPTER 3. CONFIGURATION ..................... 3-1 ......................3-4 ESET ONFIGURATION CHAPTER 4.
  • Page 4 Table Of Contents SDRAM I ....................... 6-25 NITIALIZATION CHAPTER 7. C790 BUS / G-BUS BRIDGE ..................7-1 ......................... 7-1 NTRODUCTION ................7-2 DDRESS PACE ECODE AND RANSLATION ......................... 7-2 RANSACTIONS ..........................7-3 NDIANNESS ..........................7-4 RRORS ..........................7-5 EGISTERS 7.6.1 System Configuration Register ....................
  • Page 5 Table Of Contents 8.2.12 Reset........................... 8-16 8.2.13 Retry requests ........................8-17 PGB M ....................... 8-18 EMORY 8.3.1 PCI Configuration Registers....................8-18 8.3.2 PGB G-Bus Registers......................8-20 ...................... 8-30 EGISTER ORTING 8.4.1 pgbCSR[1] Dual Porting ....................8-30 8.4.2 p2gBase[3] Dual Porting ....................8-30 8.4.3 Protection Strategy ......................
  • Page 6 Table Of Contents 9.2.3 Source Address Registers (SAR0 - SAR7) ................9-14 9.2.4 Destination Address Register (DAR0 - DAR7) ..............9-15 9.2.5 Byte Count Register (BCR0 – BCR7)................. 9-15 9.2.6 Next Record Pointer Registers (NRPR0 – NRPR7) ............9-16 9.2.7 Global Control and Status Register (GCSR) ..............
  • Page 7 Table Of Contents 12.5.2 FIFO Operation....................... 12-45 12.5.3 MII Interface........................12-49 12.5.4 Interrupt........................... 12-49 12.5.5 Reset..........................12-49 CHAPTER 13. REMOVED ......................... 13-1 CHAPTER 14. UARTS WITH FIFOS ....................14-1 14.1 ..........................14-1 VERVIEW 14.1.1 Key Features........................14-2 14.1.2 Introduction ........................14-2 14.2 ....................
  • Page 8 ......................15-17 YSTEM RRORS 15.10 ...................... 15-17 NTERRUPT ENERATION 15.10.1 Compatibility Mode ......................15-17 15.10.2 Toshiba Mode ......................... 15-18 15.10.3 Interrupt Generation on TSIC0 ..................15-18 CHAPTER 16. CLOCKS ........................16-1 16.1 ..........................16-1 VERVIEW 16.2 ..........................16-2 EATURES 16.3 ..........................
  • Page 9 Table Of Contents TABLE OF FIGURES 3-1 TX7901 B ....................... 3-1 IGURE LOCK IAGRAM 3-2 A TX7901..................3-3 IGURE TYPICAL SYSTEM UTILIZING 4-1 M .......................... 4-1 IGURE EMORY 5-1 C790 B ......................5-2 IGURE LOCK IAGRAM 6-1 T ......................6-2 IGURE STAGE ECODING...
  • Page 10 Table Of Contents 15-1 SPI M ....................... 15-2 IGURE EMORY 15-2 TSEI B ......................15-7 IGURE LOCK IAGRAM 15-3 CPHA E .................. 15-9 IGURE QUALS RANSFER ORMAT 15-4 CPHA E ................15-10 IGURE QUALS RANSFER ORMAT 15-5 MCU I ..................... 15-11 IGURE NTERFACE IGNALING...
  • Page 11 Table Of Tables TABLE OF TABLES 4-1 L 7901 D ....................4-3 ABLE IST OF EVICE EGISTERS 6-1 I ....................6-6 ABLE NITIAL ALUES AFTER ESET 6-2 E DIMM ..................6-6 ABLE XAMPLE ALUES FOR 6-3 L SDRAM M ............... 6-7 ABLE IST OF EMORY...
  • Page 12 Table Of Tables 8-17 P ......................8-30 ABLE ROTECTION EVELS 8-18 E PGB C I/O P ........8-35 ABLE NABLES FROM ORE TO ISTED LPHABETICALLY 8-19 C I/O P ......8-35 ABLE ONTROL AND ADS TO ISTED LPHABETICALLY 8-20 C &...
  • Page 13 Table Of Tables 12-7 CCR ................. 12-8 ABLE EGISTER IELD ESCRIPTIONS 12-8 TFCR ................12-9 ABLE EGISTER IELD ESCRIPTIONS 12-9 RFCR ................12-12 ABLE EGISTER IELD ESCRIPTIONS 12-10 R 0 ................12-13 ABLE ECEIVE ODES WHEN LL IS 12-11 TSR ................
  • Page 14 Handling Precautions...
  • Page 16 It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property.
  • Page 17 1 Using Toshiba Semiconductors Safely...
  • Page 18 2 Safety Precautions 2. Safety Precautions This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. Please be sure that you understand the meanings of the labels and the graphic symbol described below before you move on to the detailed descriptions of the precautions.
  • Page 19 2 Safety Precautions General Precautions regarding Semiconductor Devices Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury. Do not insert devices in the wrong orientation.
  • Page 20 2 Safety Precautions Precautions Specific to Each Product Group 2.2.1 Optical semiconductor devices When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. This is highly likely to impair vision, and in the worst case may cause blindness. If it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropriate type of laser protective glasses as stipulated by IEC standard IEC825-1.
  • Page 21 2 Safety Precautions Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fire or explode, resulting in fire or injury.
  • Page 22 3 General Safety Precautions and Usage Considerations 3. General Safety Precautions and Usage Considerations This section is designed to help you gain a better understanding of semiconductor devices, so as to ensure the safety, quality and reliability of the devices which you incorporate into your designs. From Incoming to Shipping 3.1.1 Electrostatic discharge (ESD)
  • Page 23 3 General Safety Precautions and Usage Considerations (e) Make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) Make sure that jigs and tools used in the assembly process do not touch devices. (g) In processes in which packages may retain an electrostatic charge, use an ionizer to neutralize the ions.
  • Page 24 3 General Safety Precautions and Usage Considerations • When storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate from one other and do not stack them directly on top of one another.
  • Page 25 3 General Safety Precautions and Usage Considerations Storage 3.2.1 General storage • Avoid storage locations where devices will be exposed to moisture or direct sunlight. • Follow the instructions printed on the device cartons regarding transportation and storage. Temperature: Humidity: •...
  • Page 26 3 General Safety Precautions and Usage Considerations • If the 12-month storage period has expired, or if the 30% humidity indicator shown in Figure 1 is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at high temperature to remove any moisture.
  • Page 27 For more detailed information about each product family, refer to the relevant individual technical datasheets available from Toshiba. 3.3.1 Absolute maximum ratings Do not use devices under conditions in which their absolute maximum ratings (e.g.
  • Page 28 3 General Safety Precautions and Usage Considerations Since the details regarding the handling of unused pins differ from device to device and from pin to pin, please follow the instructions given in the relevant individual datasheets or databook. CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open, it can easily pick up extraneous noise and become unstable.
  • Page 29 For details of how to interface particular devices, consult the relevant technical datasheets and databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba office or distributor.
  • Page 30 3 General Safety Precautions and Usage Considerations 3.3.10 Decoupling Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 Ω...
  • Page 31 3 General Safety Precautions and Usage Considerations the thickness of the power supply wiring patterns on the printed circuit board. One effective method, for example, is to devise several shielding options during design, and then select the most suitable shielding method based on the results of measurements taken after the prototype has been completed.
  • Page 32 3 General Safety Precautions and Usage Considerations 3.4.2 Inspection Sequence Do not insert devices in the wrong orientation. Make sure that the positive and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode, resulting in injury to the user.
  • Page 33 3 General Safety Precautions and Usage Considerations (1) Lead insertion hole intervals on the printed circuit board should match the lead pitch of the device precisely. (2) If lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads.
  • Page 34 3 General Safety Precautions and Usage Considerations (1) Using a soldering iron Complete soldering within ten seconds for lead temperatures of up to 260°C, or within three seconds for lead temperatures of up to 350°C. (2) Using medium infrared ray reflow •...
  • Page 35 3 General Safety Precautions and Usage Considerations • For surface-mount packages, complete soldering within 5 seconds at a temperature of 250°C or less in order to prevent thermal stress in the device. • Figure 5 shows an example of a recommended temperature profile for surface-mount packages using solder flow.
  • Page 36 (2) When handling chips, be careful not to expose them to static electricity. In particular, measures must be taken to prevent static damage during the mounting of chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted).
  • Page 37 Two recommended silicone compounds in which base oil separation is not a problem are YG6260 from Toshiba Silicone. (6) Heat-sink-equipped devices can become very hot during operation. Do not touch them, or you may sustain a burn.
  • Page 38 3 General Safety Precautions and Usage Considerations Protecting Devices in the Field 3.6.1 Temperature Semiconductor devices are generally more sensitive to temperature than are other electronic components. The various electrical characteristics of a semiconductor device are dependent on the ambient temperature at which the device is used. It is therefore necessary to understand the temperature characteristics of a device and to incorporate device derating into circuit design.
  • Page 39 3 General Safety Precautions and Usage Considerations 3.6.6 Interference from light (ultraviolet rays, sunlight, fluorescent lamps and incandescent lamps) Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases the device can malfunction. This is especially true for devices in which the internal chip is exposed.
  • Page 40 (1) Using resonators which are not specifically recommended for use Resonators recommended for use with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions. If you use a resonator not included in this list, please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application.
  • Page 41 4 Precautions and Usage Considerations...
  • Page 42 TX7901 User’s Manual Rev. 6.30T November, 2001 DOCUMENT NUMBER M−99−00004−07...

  • Page 44: Chapter 1. Introduction

    1. Introduction 1.1 Overview The TX7901 MIPS RISC microcontroller is a highly integrated solution based on Toshiba’s dual-issue super-scalar pipeline Processor Core, the C790 (henceforth referred to as “the C790”). The C790 has a 128-bit internal architecture featuring MIPS ISA support and additional instruction enhancements specially developed for embedded applications.
  • Page 45 Fiber Physical Medium Dependent PMD (EMAC) Floating Point Unit G-Bus Proprietary Toshiba On-chip Bus Interface intended for IP interfaces Instruction Cache Memory Integrated Circuit Intellectual Property – proprietary circuit implementations from multiple vendors intended to be incorporated into a larger IC design...

  • Page 46: Other Terminology

    Chapter 1: Introduction Read/Write Receive Self-Clearing To Be Determined TP-PMD Twisted Pair-Physical Medium Dependent Time Slot Transmit UCAB Un-cached Accelerated Buffer UART Universal Asynchronous Receiver/Transmitter VAddr Virtual Address Write-Back Buffer Write-Only 1.2.2 Other Terminology To Assert a signal means to take it to its active level. An active high signal is “1” when asserted, and an active low signal is “0”...
  • Page 47 Chapter 2: Features 2. Features C790 integrated high-performance RISC processor core with 128-bit internal architecture optimized for high data throughput • 2-way super-scalar pipeline with 128-bit (2x64-bit) data path • 200/266 MHz operation • MIPS I, II, III compatible ISA with selected MIPS IV ISA (Pre-fetch and Move Conditional Instructions) •...
  • Page 48 Chapter 2: Features PCI/G-Bus Bridge (“PGB”) • Fully compliant with PCI Local Bus Specification Rev. 2.1 • 32-bit PCI bus interface • 33 MHz or 66 MHz PCI operation • Zero-Latency Back to Back transfers • Supports on-chip arbitration of up to 5 masters (supports a maximum of 2 - 4 external PCI devices) •...
  • Page 49 Chapter 2: Features Interrupt Controller The Interrupt controller in the TX7901 supports both internal and external interrupts to the C790 core. It contains an interrupt source register to identify up to 22 different interrupt sources. In addition, there is an interrupt register mask that is used to mask interrupt sources to the C790. The supported Interrupts are: •...

  • Page 50: Tx7901 Block

    Chapter 3: Configuration 3. Configuration The following is the block diagram of the TX7901: Test Logic C790 Bus (128-bit Internal System Bus) I$32K D$32K SDRAM Controller DEBUG 64-Bit G-Bus DMAC Bridge C790 64-bit Internal INTC G-Bus Timers SPI Serial Dual Dual Boot UARTs...
  • Page 51 Chapter 3: Configuration C790 High performance MIPS RISC processor core with 128-bit internal system bus interface. Dual 10/100Mbps Ethernet MAC with scatter-gather DMA bus master capability. PCI Bridge 32-bit PCI bus interface compliance with PCI Local Bus Specification Rev. 2.1. PCI0 is 66 MHz/32-bit PCI.

  • Page 52: Figure 3-2 Atypical System Utilizing

    Chapter 3: Configuration Test Logic 200/266 MHz* 128b/ 100 MHz SDRAM Memory 133 MHz Devices SDRAMC PC100/133 DIMM I$ 32K D$ 32K 64-Bit G- DMAC DEBUG Bus Bridge Note: 266 MHz CPU and PC 133 C790 SDRAM interfaces are being planned as premium products.

  • Page 53: R Eset C Onfiguration

    Chapter 3: Configuration 3.1 Reset Configuration C790: Pins define the endianness. SPI: 2 MHz (133)/1.56 MHz (100) of the bit rate accesses Boot ROM. SDRAM: 8 MB per DIMM (chip select) starting at physical address 0x0000_0000. TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

  • Page 54: Figure 4-1 Memory Map

    Chapter 4: Address Maps 4. Address Maps 4.1 Memory Map The physical memory space of the TX7901 is 4 GB. The memory management unit (MMU) of the C790 manages the memory map of the TX7901. The TX7901 virtual and physical addresses are both 32 bits wide.

  • Page 55: Register Map

    Chapter 4: Address Maps TX7901 internal registers are mapped from 0x1E00_0000 to 0x1EFF_FFFF (16 MB). The ROM/SRAM addresses are mapped from 0x1F00_0000 to 0x20FF_FFFF (32 MB). Main memory space (SDRAM) can be located anywhere except in the internal register range. This memory space is located on the C790 Bus.

  • Page 56: Table 4-1 List Of 7901 Device

    Chapter 4: Address Maps The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information. Table 4-1 List of 7901 Device Registers Name Register Description Address...
  • Page 57 Chapter 4: Address Maps The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information. Name Register Description Address Size(b) NRPR3 Channel 3 Next Record Pointer Register 0x1E00_1350 RESERVED...
  • Page 58 Chapter 4: Address Maps The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information. Name Register Description Address Size(b) GCLMA0 GC Lower MEM Address 0 0x1E00_2098 GCUMA1...
  • Page 59 Chapter 4: Address Maps The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information. Name Register Description Address Size(b) PgbCSR PGB Control and Status Register 0x1E00_3100 g2pLower0...
  • Page 60 Chapter 4: Address Maps The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information. Name Register Description Address Size(b) Dual Ethernet Media Access Controllers, Base Addresses 0x1E00_5000 and 0x1E00_6000 (Note: Counters start at offsets 0x200) Reserved 0x1E00_5000...
  • Page 61 Chapter 4: Address Maps The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information. Name Register Description Address Size(b) SCCnt0 Single Collision 0x1E00_5278 EDCnt0...
  • Page 62 Chapter 4: Address Maps The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information. Name Register Description Address Size(b) TIReg1 Transmit Interrupt Register 0x1E00_6038 RIMReg1...
  • Page 63 Chapter 4: Address Maps The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information. Name Register Description Address Size(b) RxFrame511_1 Frames Received (RxFrame511) 0x1E00_62D8 RxFrame1K1...
  • Page 64 Chapter 4: Address Maps The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information. Name Register Description Address Size(b) DLM1 Divisor Latch 1 (MS) 0x1E00_8004 IIR1...
  • Page 65 Chapter 4: Address Maps The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information. Name Register Description Address Size(b) g2pUpper1 g2pwindow Upper Address Register 1 0x1E00_A120 g2pLower2...

  • Page 66: Chapter 5. C790 Processor Core

    Chapter 5: C790 Processor Core 5. C790 Processor Core This chapter is an overview of the C790 Processor Core. 5.1 Features The C790 is an integrated, high-performance, RISC processor core with 128-bit internal data paths optimized for high data throughput. Some of the C790 features are listed below: 2-way super-scalar pipeline with 128-bit (2x64-bit) data path 200/266 MHz operation...

  • Page 67: C790 Block

    Chapter 5: C790 Processor Core Block Diagram and Functional Block Descriptions This section shows a block diagram of the C790 and summarizes the modules’ functionality. Instruction Virtual Address PC Unit (IVA) Instruction Cache (I-Cache) PC Pipe & Tag, BHT, Predecode, Inst RAMs BTAC (32kB, 2-way set assoc.) ITLB...
  • Page 68 Chapter 5: C790 Processor Core PC Unit: The 32-bit Program Counter (PC) holds the address of the instruction that is being executed. It also contains a 64-entry Branch Target Address Cache (BTAC) which stores branch target addresses used for branch prediction (to eliminate branch penalties).

  • Page 69: C790 R Egisters

    Chapter 5: C790 Processor Core The C790 extends the normal MIPS-compatible register set by extending the width of the general purpose registers (GPRs) from 64 bits to 128 bits. It also incorporates an additional pair of HI/LO registers for the I1 pipe, and the SA register for funnel shift instructions. 5.3 C790 Registers The C790 has 128-bit wide GPRs.

  • Page 70: Floating Point Unit

    Chapter 5: C790 Processor Core • Data order for block reads: Sequential ordering • Data order for block writes: Sequential ordering • Instruction cache miss restart: After all data are received • Data cache miss restart: Early restart on first quad-word •...

  • Page 71: D Ebug F Unctions

    Chapter 5: C790 Processor Core 5.9 Debug Functions The C790 supports ranged hardware break pointers with mask registers. This makes it possible to debug with less observational impact. Note that C790 debugging also supports software debugging using the BREAK instruction as defined in MIPS ISA. Features: •...

  • Page 72: Chapter 6. Sdram Memory Controller

    Chapter 6: SDRAM Memory Controller 6. SDRAM Memory Controller 6.1 Overview This SDRAM Controller is used to connect the C790 (128-bit MIPS CPU) to SDRAM. The SDRAM devices that can be connected are 64 Mb, 128 Mb, or 256 Mb with a 4-bank architecture.

  • Page 73: Figure 6-1 Two-Stage Decoding

    Chapter 6: SDRAM Memory Controller registers. This value must match exactly. This value effectively sets a 256 MB region. • sysAddr[27:20] are compared against bits [27:20] in the LOW Decoder registers. This value of sysAddr must be greater than or equal to the LOW decode value. This describes the low boundary for the region.

  • Page 74: Figure 6-2 Initial Setting After

    Chapter 6: SDRAM Memory Controller 0xFFFF_FFFF 0x0FFF_FFFF 0x0200_0000 D3 HIGH DIMM3 (8 MB) D3 LOW 0x0180_0000 D2 HIGH DIMM2 (8 MB) D2 LOW 0x0100_0000 D1 HIGH DIMM1 (8 MB) D1 LOW 0x0080_0000 D0 HIGH DIMM0 (8 MB) 0x1000_0000 D0 LOW 0x0000_0000 Region0 0x0000_0000...
  • Page 75 Chapter 6: SDRAM Memory Controller BankAddr[1:0] Address[12:0] DIMM0 RAS, CAS, WE • sdmCSB[0] DIMM1 • sdmCSB[1] DIMM2 • sdmCSB[2] DIMM3 • sdmCSB[3] data [63:0] check bits[7:0] DQM[7:0] RefClk TX7901 100/133 MHz Clock Distribution Figure 6-3 Example Connection of Single-sided DIMMs TX7901 User’s Manual (Rev.
  • Page 76 Chapter 6: SDRAM Memory Controller BankAddr[1:0] Address[12:0] DIMM0,2 RAS, CAS, WE • sdmCSB[0] • sdmCSB[1] DIMM1,3 sdmCSB[2] • sdmCSB[3] 8b 8b data [63:0] check bits[7:0] DQM[7:0] RefClk TX7901 100/133 MHz Clock Distribution Figure 6-4 Example Connection of Double-sided DIMMs TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

  • Page 77: Table 6-1 Initial Values After

    Chapter 6: SDRAM Memory Controller 6.4.1 Default Memory Map After sysResetB is active, the default memory map is as shown in Table 6-1. Table 6-1 Initial Values after Reset Initial Device HIGH Size DIMM0 sdrCSB[0] D0LOW (0x0 000_0000) D0HIGH (0x0 07F_FFFF) 8 MB DIMM1 sdrCSB[1]...

  • Page 78: R Egisters

    Chapter 6: SDRAM Memory Controller 6.5 Registers The following table is a register map of the SDRAM Memory Controller Module. Table 6-3 List of SDRAM Memory Controller Registers Name Register Description Address Size(b) SDRAM Memory Controller, Base Address 0x1E00_0000 D0PR DIMM 0 Parameters Register 0x1E00_0000 D1PR...

  • Page 79: Egisters

    Chapter 6: SDRAM Memory Controller SDRAMC Physical Address sdmCSB[0] DIMM0 D0PR D0LOW General Control D0HIGH DIMM1 sdmCSB[1] DOMR D1PR DREFRESH D1LOW D1HIGH DDRIVE DIMM2 sdmCSB[2] D2PR D2LOW D2HIGH DIMM3 sdmCSB[3] D3PR D3LOW D3HIGH DEMR DEESR DEEAR Figure 6-5 SDRAM Registers TX7901 User’s Manual (Rev.

  • Page 80: Parameters Register

    Chapter 6: SDRAM Memory Controller All of the following registers are 128 bits wide and are aligned to 16 Byte boundaries. In order to facilitate Bi-Endian programming, it is strongly recommended to use lq/sq to access these registers. 6.5.1 Parameters register 31 30 29 28 26 25 24 23...

  • Page 81: Figure 6-6 Example Timingp

    Chapter 6: SDRAM Memory Controller Timing Field Bit(s) Description Symbol Refresh Recovery Time (110) These bits specify the earliest timing for a new command after a Refresh command. 001 : 5 clock cycles 010 : 6 clock cycles 28:26 tRFC 011 : 7 clock cycles 100 : 8 clock cycles 101 : 9 clock cycles...
  • Page 82 Chapter 6: SDRAM Memory Controller DIMM 1 Parameters Register (0x1E00_0010) Field Description Device Select (01) 00 : 16 Mb SDRAM 01 : 64/128 Mb SDRAM 10 : 256 Mb SDRAM 11 : Reserved – 31:2 Reserved Other parameters use the same values as DIMM 0. DIMM 2 Parameters Register (0x1E00_0020) Field Description...

  • Page 83: Operation Mode Register (0X1E00_0040) R/W

    Chapter 6: SDRAM Memory Controller DIMM 3 Parameters Register (0x1E00_0030) Field Description Device Select (01) 00 : 16 Mb SDRAM 01 : 64/128 Mb SDRAM 10 : 256 Mb SDRAM 11 : Reserved – 31:2 Reserved Other parameters use the same values as DIMM 0. 6.5.2 Operation Mode Register (0x1E00_0040) R/W 13 12 10 9...
  • Page 84 Chapter 6: SDRAM Memory Controller In order to execute one of the above commands on the SDRAM, the following procedure should occur: 1. The corresponding value should be written to the SDRAM Operation Mode Register. 2. OMR Write should be followed by a dummy write to the corresponding SDRAM. For Mode Register Write, the RAS address [12:0] will be put in the Mode Register.

  • Page 85: Sdram Mode Register

    Chapter 6: SDRAM Memory Controller 3. Store dummy data (32-bit) to a location. The address of this store instruction is saved in the Mode Register as data. The address is shuffled by address mapping. The corresponding address bit may vary according to the SDRAM chip and DIMM connection. SDRAMC uses RA[12:0] of sysAddr as a Mode Register value.

  • Page 86: Ecc Mode Register (0X1E00_0050) R/W

    Chapter 6: SDRAM Memory Controller 6.5.3 ECC Mode Register (0x1E00_0050) R/W 16 15 Check Field Bit(s) Description Error Correction Check Mode (000) 000 : ECC Disable Mode, no check bit generation 001 : Detect mode. Performs check bit generation during memory writes and error detection only during memory reads.

  • Page 87: Ecc Error Status Register (Read Only) (0X1E00_0060)

    Chapter 6: SDRAM Memory Controller 6.5.4 ECC Error Status Register (read only) (0x1E00_0060) 24 23 16 15 Syndr Check When there is an ECC Error (single or double bit error), the failing status is stored in this register and an interrupt is generated. After an ECC Error, the ECC Error Status Register and the ECC Error Address Register keep the status and address of the latest error until it has been read.

  • Page 88: Ecc Error Address Register (Read Only) (0X1E00_0070)

    Chapter 6: SDRAM Memory Controller 6.5.5 ECC Error Address Register (read only) (0x1E00_0070) ErrAddr When there is an ECC Error, the failing address is stored in this register. This register keeps the error address of the latest ECC error. Field Bits Description ErrAddr...

  • Page 89: Sdram Interface Output Drive-Strength Control Register (0X1E00_00A0) R/W

    Chapter 6: SDRAM Memory Controller 6.5.7 SDRAM Interface Output Drive-Strength Control Register (0x1E00_00A0) R/W This register contains parameters which are used to select the SDRAM interface control/address (i.e. CSB[3:0], CKE, RASB, CASB, WEB, BA[1:0], and AD[12:0]) and data/data-mask (i.e. CB[7:0], DQ[127:0], and DQM[15:0]) output drive-strength. Field Bits Description...

  • Page 90: Dimm 0 High Address Decode (0X1E00_0110)

    Chapter 6: SDRAM Memory Controller 6.5.9 DIMM 0 HIGH Address Decode (0x1E00_0110) 28 27 20 19 DIMM 0 HIGH boundary 1 ------------------------------------------------------------1 4 (R/O) Bits Description 31:28 DIMM 0 27:20 HIGH Boundary 19:0 6.5.10 DIMM 1 LOW Address Decode (0x1E00_0120) 28 27 20 19 DIMM 1...

  • Page 91: Dimm 2 Low Address Decode (0X1E00_0140)

    Chapter 6: SDRAM Memory Controller 6.5.12 DIMM 2 LOW Address Decode (0x1E00_0140) 28 27 20 19 DIMM 2 LOW boundary 0 -----------------------------------------------------------0 4 (R/W) Bits Description 31:28 DIMM 2 27:20 LOW boundary 19:0 TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) 6-20...

  • Page 92: Dimm 2 High Address Decode (0X1E00_0150)

    Chapter 6: SDRAM Memory Controller 6.5.13 DIMM 2 HIGH Address Decode (0x1E00_0150) 28 27 20 19 DIMM 2 HIGH boundary 1 ------------------------------------------------------------1 4 (R/O) Bits Description 31:28 DIMM 2 27:20 HIGH Boundary 19:0 6.5.14 DIMM 3 LOW Address Decode (0x1E00_0160) 28 27 20 19 DIMM 3...

  • Page 93: A Ddress M Apping

    Chapter 6: SDRAM Memory Controller 6.6 Address Mapping sysPAddr[27:0] is assorted into bank, row, and column addresses. This section describes the mapping of address bits for performance analysis purposes. Address range 256 MB 64 B 128 MB 64 MB 16 B = 128b 16 MB 8 B = 64 b Device size...

  • Page 94: Figure 6-7 Check Matrix For Figure 6-8 Read Modify Write

    Chapter 6: SDRAM Memory Controller 6.7 Data ECC Generation Each of the 64 data bits and 8 check bits has a unique 8-bit SECDED ECC check code; this check code is generated by taking the even parity of the ECC check code for a selected group of data bits.

  • Page 95: Ontroller

    Chapter 6: SDRAM Memory Controller sdrDQM[7:0]* outputs. The ECC data are read on the sdrCB[7:0] inputs. 2. Modify the ECC information based on the data that are to be written. The ECC nibble is modified in the SDRAM Controller. 3. Write the new data and new ECC byte. Figure 6-8 illustrates the procedure that the SDRAM Controller uses to generate ECC in a partial write to SDRAM.

  • Page 96: Sdram I Nitialization

    Chapter 6: SDRAM Memory Controller 6.8 SDRAM Initialization Following below is an example of the code used during SDRAM initialization. /* SDRAMC register definition */ #define SDRAMC 0xbe00_0000 /* SDRAMC base address(virtual) */ #define D0PR 0x0000 /* DIMM0 Parameter Register */ #define D1PR 0x0010 /* DIMM1 Parameter Register */...
  • Page 97 Chapter 6: SDRAM Memory Controller | 0 << 15 /* 3 Burst Type = Sequential | 3 << 16 /* 6:4 18:16 CAS Latency = 3 | 0 << 19 /* 8:7 20:19 OpMode = Standard Op | 0 << 21 /* 9 Write Burst Mode = programmed */\ | 0xa000_0000 /* UnCached UnMapped area for DIMM0...
  • Page 98 Chapter 6: SDRAM Memory Controller # write SDRAM chip's Mode Register t0, DOMR_WR_MODEREG t0, DOMR(k1) # write SDRAM Mode Register t2, SDRM_CL3 $0, 0(t2) # write address goes to MODE register t0, DOMR(k1) # read DOMR to make sure Write Mode Reg # It takes more than 2 x sysBusClk # start Refresh t0, SDR_RFSH...

  • Page 99: Chapter 7. C790 Bus / G-Bus Bridge

    Chapter 7: C790 Bus/G-Bus Bridge 7. C790 Bus / G-Bus Bridge 7.1 Introduction The C790 Bus/ G-Bus Bridge provides an efficient interface between the C790 bus (and its attached C790 CPU and Main Memory), and the G-Bus (and its attached peripheral devices.) The bridge supports C790 accesses to devices on the G-Bus, and G-Bus Mastering devices’...

  • Page 100: Figure 7-2 G-Bridge Address

    Chapter 7: C790 Bus/G-Bus Bridge 7.2 Address Space Decode and Translation The C790 accesses G-Bus devices through one CG internal register window, one ROM window and four PCI windows. The upper 28-bit address pAddr[31:4] seen on the C790 bus is copied directly onto the G-Bus while the lower 2–bit address is derived from the byte enable bits.

  • Page 101: Figure 7-3 Bi-Endian Support

    Chapter 7: C790 Bus/G-Bus Bridge 7.4 Endianness The C790 Bus and G-Bus support both Little and Big Endian byte ordering, while the PCI Bus only supports fixed Little Endian byte ordering. When the C790 bus is configured for the Big Endian mode via the Endianness signal, the G-Bus is configured for Big Endian as well. Bus narrowing is performed by the G-Bridge.

  • Page 102: Bu Error

    Chapter 7: C790 Bus/G-Bus Bridge 7.5 Bus Errors Bus errors occur during a bus transaction when no target device responds to the initiator within a given number of bus cycles. When a bus error occurs, the initiator terminates the transaction, signals an interrupt to the C790 and records the bad address. The target device returns to the idle state after a bus error has been detected.

  • Page 103: Table 7-1 List Of G-Bus Bridge

    Chapter 7: C790 Bus/G-Bus Bridge 7.6 Registers The registers in the G-Bus bridge are memory-mapped into the C790 address space ranging from address 0x1E00_2000 to address 0x1E00_2FFF. Table 7-1 List of G-Bus Bridge Registers (Base Address = 0x1E00_2000) Register Name Offset Size Initial Value...

  • Page 104: Table 7-2 System Configuration

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.1 System Configuration Register The System Configuration Register specifies configurations for the system. Its fields are detailed below and in Table 7-2. Table 7-2 System Configuration Register Fields Bit(s) Name Description Type Initial Value Reserved. Must be written as zeroes, 63:1 –...
  • Page 105 Chapter 7: C790 Bus/G-Bus Bridge Table 7-3 C790 Bus Control Register Fields Bit(s) Field Description Initial Value Reserved. Must be written as zeroes, and 63:7 – returns zeroes when read. 0: C790 Bus Latency Timer Enable CBLTE 1: Enable CG memory Mapping Window 3 Enable CGM3E 1: Enable 0: Disable...

  • Page 106: C790 Bus Status Register

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.3 C790 Bus Status Register The Bus Status Register reports the status of the C790 Bus. The ERR bit is set when the bridge is writing to main memory, then a C790 bus error occurs. The C790 can clear this bit by writing a “0”.

  • Page 107: C790 Bus Bad Address

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.4 C790 Bus Bad Address Register The C790 Bus Bad Address Register reports the C790 address when there is a bus error on the C790 Bus and the bridge is writing to the main memory. This register can only be set when the ERR bit in the Status register is “0”.

  • Page 108: Cg Lower Internal

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.6 CG Lower Internal Register Address (LIRA) The Lower Internal Register Address Register defines the lower internal register address for devices on the G-Bus. LIRA Table 7-7 CG Lower Internal Register Address Register Fields Bits Field Description Initial Value...

  • Page 109: Cg Lower Rom A

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.8 CG Lower ROM Address Register (LROMA) The Lower ROM Address Register defines the lower address for ROM / SRAM / external I/O devices on the G-Bus. LROMA Table 7-9 CG Lower ROM Address Register Fields Bits Field Description...

  • Page 110: Cg Upper Lower

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.10 CG Lower PCI Address Register (CGLPA0, CGLPA1, CGLPA2, CGLPA3) The CG Lower PCI Address Register defines the lower address of the CG mapping window (CGLPA0, CGLPA1, CGLPA2, CGLPA3). These addresses should be aligned to the word boundary.

  • Page 111: Gc Lower Internal

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.12 GC Lower Internal Register Address Register (GCLIRA) The Lower Internal Register Address Register defines the lower bound register address of the C790 Bus that any G-Bus master can access. GCLIOA Table 7-13 GC Lower Internal Register Address Register Fields Bits Field Description...

  • Page 112: Gc Lower Memory

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.14 GC Lower Memory Address Register (GCLMAx) The GC Lower Memory Address Register defines the lower address of the GC memory- mapping window. These addresses should be aligned to the quad-word boundary. GCLMA Table 7-15 GC Lower Memory Address Register Fields Bits Field Description...

  • Page 113: Table 7-17 G-Bus Interrupts

    Chapter 7: C790 Bus/G-Bus Bridge Table 7-17 G-Bus Interrupt Source Table Mask Event Status Mask Init. Value [31:22] Reserved [31:22] IRSTAT[21] PCI1 Reset IRMSK[21] IRSTAT[20] PCI0 Reset IRMSK[20] IRSTAT[19] External Interrupt 4 IRMSK[19] IRSTAT[18] External Interrupt 3 IRMSK[18] IRSTAT[17] External Interrupt 2 IRMSK[17] IRSTAT[16] External Interrupt 1...

  • Page 114: C790 Bus Latency

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.16 Interrupt Mask Register (IRMSK) The Interrupt Mask Register enables/disables interrupt generation. IRMSK Table 7-18 C790 Interrupt Mask Register Fields Bits Field Description Initial Value Reserved. Must be written as zeroes, and returns 63:32 – zeroes when read.

  • Page 115: Nmi Status Register

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.18 NMI Status Register (NRSTAT) The NMI Status Register reports the status of the Non-Maskable interrupt requests. An interrupt is generated if a bit in the register is set to “1.” The NMI handler analyzes the cause of the NMI and serves the request.

  • Page 116: Table 7-22 G-Bus Brokenm

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.20 G- Bus Broken Master Latency Timer The latency timer specifies the maximum period in which the master has to claim the G-bus after the G-bus is granted. The counter is decremented at every B-Bus clock cycle. The counter starts counting down when the arbiter asserts the grant signal.

  • Page 117: Table 7-24 G-Bridge Retryt

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.22 G-Bus Retry Timer The Retry timer specifies the minimum period in which the bridge can re-assert the G-Bus request signal after it receives the Retry signal and releases the G-Bus. The minimum value is 2. This timer is counted down by the G-Bus clock. Table 7-24 G-Bridge Retry Timer Fields Bits Field Description...

  • Page 118: Table 7-25 The Gc Controlr

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.23 GC Control Register The Control register enables the mapping from the G-Bus to the C790 bus. Table 7-25 The GC Control Register Fields Bit(s) Field Description Initial Value Reserved. Must be written as zeroes, and 63:6 –...

  • Page 119: Table 7-26 G-Bridge Statusr

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.24 G-Bus Status Register The Status register reports the status of the G-Bridge. The ERR bit is set when the bridge is writing to main memory, then a G-Bus error occurs. The G-Bus can clear this bit by writing a “0”.

  • Page 120: Table 7-28 G-Bus Arbiterr

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.25 G-Bus Bad Address Register The Bad Address register reports the G-Bus address when there is bus error on the G-Bus and the G-Bus bridge is writing to the device on the G-bus. This register can only be set when the ERR bit in the Status register is “0”.

  • Page 121: Table 7-29 G-Bus Arbitration

    Chapter 7: C790 Bus/G-Bus Bridge Table 7-29 G-Bus Arbitration Request Table Req [15:7] Reserved Req 6 PCI-G-Bus Bridge 1 Req 5 DMAC Req 4 Reserved Req 3 eMAC0 Req 2 eMAC1 Req 1 PCI-G-Bus Bridge 0 Req 0 G-Bridge 7.6.27 G-Bus Arbiter Granted Status Register This register indicates which G-Bus master the G-Bus is granted to.

  • Page 122: Table 7-31 G-Bus Arbiterm

    Chapter 7: C790 Bus/G-Bus Bridge 7.6.28 G-Bus Arbiter Master Status Register This register indicates the status of the current G-Bus Master. When a master is granted bus ownership, the Bus Broken Timer starts to count down. If the counter counts down to zero before the arbiter receives the gbsgHaveIt signal, the corresponding bit is set and an interrupt is generated to the C790.

  • Page 123: Chapter 8. Pci/G-Bus Bridge

    The PCI bus is an industry-standard computer bus and the G-Bus is an on-chip bus proprietary to Toshiba. The PGB maps transactions between PCI and the G-Bus. The PGB is fully compliant with the PCI 2.1 specifications with minor exceptions, which are described later.

  • Page 124: Figure 8-1 Top Level Blockd

    Chapter 8: PCI/G-Bus Bridge • Implements up to eight posted write transactions for PCI memory write commands. • Implements delayed read transactions for all PCI Master I/O and memory read commands – only one transaction at a time. • Implements “conditional” delayed read transactions for all GBUS master configuration, I/O, and memory read commands to PCI –...

  • Page 125: Ignals

    Chapter 8: PCI/G-Bus Bridge G-Bus Interface Signals PCI Interface Signals app_reset_out pgbgAddr[31:0] PCI_RST_IN* pgbgData[63:0] PCI_CLK_IN pgbgBEB7:0] PCI_GNT_IN* pgbgRdB PCI_IDSEL_IN pgbgWrB pgbgAck32B pbgbAck64B PCI_AD (32) pgbgLastB PCI_CBE_N (4) pgbgBStartB PCI_FRAME* pgbgBurstB PCI_IRDY* pgbgRetryB PCI_TRDY* pgbgBSize PCI_DEVSEL* pgbgReqB PCI_STOP* pgbgIntB_ PCI_PERR* PCI_PAR sysResetB gbsgBusClk gbsgBusErrB...

  • Page 126: Table 8-1 Signal Description

    Chapter 8: PCI/G-Bus Bridge 8.1.2 PCI / G-Bus Bridge Interface Signals Table 8-1 Signal Description Signal Name Signal Description PCI Interface Signals PCI_RST_IN* Reset PCI_CLK_IN PCI Clock PCI_GNT_IN* Bus Grant PCI_IDSEL_IN IDSEL PCI_AD (32) Address/Data PCI_CBE_N (4) Command/Byte Enable PCI_FRAME* Frame PCI_IRDY* Initiator Ready...

  • Page 127: T Heory Of O Peration

    Chapter 8: PCI/G-Bus Bridge Signal Name Signal Description gbsgLastB G-Bus Last signal In gbsgBStartB G-Bus Start In gbsgBurstB G-Bus Burst In gbsgRetryB G-Bus Retry In gbsgBSizeB G-Bus Quad-Word Count In 8.2 Theory of Operation The PGB handles read and write transactions between PCI and the G-Bus. This section describes four transaction cases.

  • Page 128: Figure 8-3 Write To Pci From

    Chapter 8: PCI/G-Bus Bridge Word Count Command Generation and Address G-Bus Decoding G-Bus Handshake Logic Retry Logic Wait Fatal State Logic Parity Status Reg. Fatal Error Interrupt Logic Parity Error Interrupt Logic Address of data in error Figure 8-3 Write to PCI from G-Bus 8.2.2 G-Bus Master Reading from PCI (Bridge Master Read) G-Bus Master reads to PCI targets can pass through one or two phases as described in the following subsections.
  • Page 129 Chapter 8: PCI/G-Bus Bridge 8.2.2.2 “Retry” Phase The PGB records the address of the current cycle along with the word count and goes into a delayed read state. The Bridge ignores new read or write transactions from the G-Bus side by issuing Retries.

  • Page 130: Figure 8-4 G-Bus Masterr

    Chapter 8: PCI/G-Bus Bridge Word Count Command Generation Address Decode G-Bus G-Bus Handshake Logic Fatal Retry Logic Wait State Logic Status Reg. Parity Fatal Error Interrupt Logic Parity Error Interrupt Logic Figure 8-4 G-Bus Master Read from PCI Retry until matching G-Bus cycle detected TIme Out...

  • Page 131: Table 8-2 G-Bus Burst Sizes

    Chapter 8: PCI/G-Bus Bridge 8.2.3 PCI Master Writing to G-Bus Slave (Bridge Target Write) The PGB performs posted writes for all memory and I/O write transactions to the G-Bus. PCI configuration transactions to the PGB are not forwarded to the G-Bus. Although PCI bursts may be of arbitrary length, burst transactions on the G-Bus can only have “packet”...

  • Page 132: Pci Master Reading From G-Bus Slave (Bridge Target Read)

    Chapter 8: PCI/G-Bus Bridge Word Count Address Generation and Data Folding to 32 bits for 32 bit Slaves G-Bus G-Bus Handshake Logic Retry Logic Fatal Wait State Logic Status Reg. Parity Fatal Error Interrupt Logic Parity Error Interrupt Logic Figure 8-6 PCI Master Writing to the G-Bus 8.2.4 PCI Master Reading from G-Bus Slave (Bridge Target Read) The core implements a delayed read strategy as described below.

  • Page 133: Table 8-3 Supported Pci

    Chapter 8: PCI/G-Bus Bridge Word Count Address Generate and Data un- Folding to 32 bits for 32-bit Slaves G-Bus Handshake Logic G-Bus Retry Logic Wait State Logic Fatal Status Reg. Fatal Error Interrupt Parity Logic Parity Error Interrupt Logic Figure 8-7 PCI Master Reading from G-Bus 8.2.5 Doorbell Feature The PGB G-Bus Command and Status register has an interrupt bit that may be set by a PCI Master requiring attention from resources on the G-Bus.

  • Page 134: Figure 8-8 G-Bus To Pci Address

    Chapter 8: PCI/G-Bus Bridge C/BE# Transaction Type PCI to G-Bus G-Bus to PCI 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple Yes* 1101 Dual-Address Cycle 1110 Memory Read Line Yes* 1111 Memory Write and Invalidate Yes* *g2pCycleType.type[n] may only be set to the value 0x6 to perform a “memory read multiple”...

  • Page 135: Pci To G-Bus Address Mapping

    Chapter 8: PCI/G-Bus Bridge 8.2.9 PCI to G-Bus Address Mapping The PGB performs PCI to G-Bus address mapping using the mechanism shown in the figure below. Pulled from inside core. PCI.hit[0] GBUS Map PCI.hit[1] PCI Map CORE PCI.hit[2] PCI.I/O.hit[0] membase[0] membase[1] membase[2] I/O base[0]...

  • Page 136: Figure 8-10 Transactions With A

    Chapter 8: PCI/G-Bus Bridge reported to the PCI Master for PCI Master write operations. G-Bus errors are reported to the PCI Master for PCI Master read operations by an abort. G-Bus errors will be reported on the PCI Bus as a Target Abort regardless of whether this transaction has appeared on the G- Bus or not.

  • Page 137: Pci Bus Arbiter

    Chapter 8: PCI/G-Bus Bridge 8.2.11 PCI Bus Arbiter The PCI Bus Arbiter supports up to five Masters on the PCI Bus, including the PGB. The Arbiter may be enabled or disabled through the G-Bus to allow an external arbiter to be used. 8.2.11.1 PCI Bus Priority All masters have the same round robin priority.

  • Page 138: Reset

    Chapter 8: PCI/G-Bus Bridge PCI0 PCI0_ReqB PCI0_ReqB PCIO_GntB PCI0_GntB Req0 Gnt0 PCI0_Gnt0B Req1 PCI0_Req1B Gnt1 PCI0_Gnt1B Req2 PCI0_Req2B Gnt2 PCI0_Gnt2B Req3 PCI0_Req3B_ PCI1_Req1B Gnt3 PCI0_Req4B_ PCI1_Req2B Req4 Gnt4 Req1 PCI0_Gnt3B_ PCI1_Gnt1B Gnt1 Req2 PCI0_Gnt4B_ PCI1_Gnt2B Gnt2 PCI1 Req0 Gnt0 PCI1_ Gnt0B PCI1_ ReqB PCI1_ReqB PCI1_GntB...

  • Page 139: Retry Requests

    Chapter 8: PCI/G-Bus Bridge Satellite. This bit should not be changed dynamically by the application, which could cause the system to read the wrong PCI config space and disable certain operations. 8.2.12.1.1 Satellite Mode If the PGB is operating in the “Satellite Mode”, the PCI target Interface is disabled after reset except to Configuration Space access cycles on the PCI Bus.

  • Page 140: Pgb Memory Map

    Chapter 8: PCI/G-Bus Bridge 8.3 PGB Memory Map The PGB uses a number of memory mapped regions on the G-Bus to provide access to PCI resources. These are controlled and configured through a number of PGB registers mapped into the G-Bus address space. This section describes the registers used to control and configure the PGB.
  • Page 141 Chapter 8: PCI/G-Bus Bridge 8.3.1.1 PCI Base Address Block Sizes Table 8-5 shows the PCI window sizes. Table 8-5 PCI Window Sizes Size Corresponding PCI Configuration Address Type (bytes) G-Bus Window IO Base Address[0] p2gwindow3 Memory Base Address[2], 20h, 24h Memory p2gwindow2 Memory DAC Base Address[2]...

  • Page 142: Pgb G-Bus Registers

    Chapter 8: PCI/G-Bus Bridge 8.3.2 PGB G-Bus Registers The control and configuration registers for the PGB are memory mapped into the G-Bus address space through a 4 KB range located at [0x1E00_3000] through [0x1E00_3FFF]. A chip select signal selects the Configuration register space during address decoding of G-Bus target cycles to the Configuration registers.
  • Page 143 Chapter 8: PCI/G-Bus Bridge 8.3.2.1 PGB Control and Status Register (pgbCSR ) The pgbCSR Register provides overall control and status for the PGB. Ten bits provide control and status. Bits[23:16] are the latency timer for G-Bus delayed reads. G-Bus Access to this register is allowed using the G-Bus single cycle mode.
  • Page 144 Chapter 8: PCI/G-Bus Bridge 8.3.2.2 G-Bus to PCI Memory Address Window Registers The G-Bus access PCI locations through G-Bus memory address windows called g2pwindows. Each g2pwindow is defined by four registers: g2pUpper, g2pLower, g2pBase, and g2pCycleType. The PGB provides four G2Pwindows. The four g2pUpper and g2pLower register pairs are compared to the current G-Bus address on each Gbstart cycle.
  • Page 145 Chapter 8: PCI/G-Bus Bridge 8.3.2.2.1 g2pUpper Address Registers (g2pUpper0, g2pUpper1, g2pUpper2, g2pUpper3) The functionality of these registers is described in Section 8.3.2.2 above. The fields of these registers are further detailed in the following figure and Table 8-8. g2pUpper [31:3] Table 8-8 g2pUpper Address Register Field Definitions Bit(s) Field...
  • Page 146 Chapter 8: PCI/G-Bus Bridge 8.3.2.2.3 g2pBase Address Registers (g2pBase0, g2pBase1, g2pBase2, g2pBase3) The functionality of these registers is described in Section 8.3.2.2 above. The fields of these registers are further detailed in the following figure and Table 8-10. g2pBase [63:32] g2pBase [31:3] Table 8-10 g2pBase Address Register Field Descriptions Bit(s)
  • Page 147 Chapter 8: PCI/G-Bus Bridge Bit(s) Field Description e[1] Enable for g2pWindow[1]. Cleared during reset. (0) – Reserved (0) Assigned to PCI C/BE[3:1]* during the PCI address phase through 10:8 type[1] g2pWindow[1]. Cleared during reset. (0) – Reserved. Read back as “0”. (0) e[0] Enable for g2pWindow[0].
  • Page 148 Chapter 8: PCI/G-Bus Bridge 8.3.2.3 PCI to G-Bus Memory Windows The PCI accesses G-Bus locations through PCI memory windows called p2gwindows. Each p2gwindow is defined by the normal PCI base register mechanism. The PGB provides four PCI base registers; three DAC memory base pairs, and a single I/O base. These PCI base registers allow for four individual p2gwindows.
  • Page 149 Chapter 8: PCI/G-Bus Bridge 8.3.2.4 Bi-Endian support The following registers support the Bi-Endian feature. 8.3.2.4.1 g2pSwapCtrl The g2pSwapCtrl Register controls the Byte Swapper in the data path from the G-Bus to the PCI Bus. The PCI Bus is always Little Endian. The Byte Swapper aligns the byte stream when the CPU is in the Big Endian mode.
  • Page 150 Chapter 8: PCI/G-Bus Bridge 8.3.2.4.2 p2gSwapCtrl The p2gSwapCtrl Register controls the Byte Swapper in the data path from the PCI Bus to the G-Bus. The PCI Bus is always Little Endian. The Byte Swapper aligns the byte stream when the CPU is in the Big Endian mode.
  • Page 151 Chapter 8: PCI/G-Bus Bridge 8.3.2.4.3 regSwapCtrl The regSwapCtrl Register controls the Byte Swapper in the data path from the G-Bus to the PGB registers. The regSwapper cancels the effect of the p2gSwapper when the CPU is in the Big Endian mode and the p2gSwapper is enabled. Access from the external master on the PCI Bus to the PGB register is always non-swapped.

  • Page 152: Table 8-17 Protection Levels

    Chapter 8: PCI/G-Bus Bridge 8.4 Register Dual-Porting The configuration registers of the PGB consist of two groups; namely, the PCI configuration register group and the G-Bus configuration register group. The G-Bus configuration register group is used to configure the G-Bus interface of the PGB and is accessible at all times from the G-Bus.

  • Page 153: Pci Core

    Chapter 8: PCI/G-Bus Bridge 8.5 PCI Core 8.5.1 Overview This section describes the TX7901’s PCI core with FIFOs. It covers the 66 MHz Asynchronous Host Bridge and Satellite cores. 8.5.2 Features The TX7901’s PCI Host Bridge and Satellite core provide the following major features: •...

  • Page 154: A Rchitecture

    Chapter 8: PCI/G-Bus Bridge 8.6 Architecture 8.6.1 Major Internal Modules This section identifies the main blocks comprising the PCI core. These blocks are listed below and shown in Figure 8-12. Each core provides eight-location dual-port FIFOs to buffer all data paths between the G-Bus and the PCI bus. Master Write FIFO Stores data from the G-Bus for Master Write cycles.

  • Page 155: Figure 8-12 High Levela

    Chapter 8: PCI/G-Bus Bridge CORE Block Multiplexer Master Register Write FIFO Multiplexer Target PCI ADOUT Register Read FIFO Register To G-Bus Register Master and Target Interface PCI.AD Blocks Configuration Control Registers Master Read FIFO PCI Bus Register Target Write FIFO Target Command Address...

  • Page 156: I/O Signals For Pci Core

    Chapter 8: PCI/G-Bus Bridge 8.6.2 I/O Signals for PCI Core This section identifies the input and output signals for the PCI core with FIFOs. In Figure 8-13, PCI bus interface signals are shown on the left, and G-Bus interface signals are on the right.

  • Page 157: Table 8-18 Enables From Pgb C

    Chapter 8: PCI/G-Bus Bridge 8.6.2.1 PCI Bus Interface Signal List The tables in this section describe the PCI bus interface signals for the 32-bit PCI to 64-bit application core. Signal names ending with “*” are Active Low. Table 8-18 Enables from PGB Core to I/O Pads, Listed Alphabetically Signal Width Description...

  • Page 158: Trdy_Timeout

    Chapter 8: PCI/G-Bus Bridge 8.6.3 TRDY_TIMEOUT Lock up could occur if the requested PCI Target responds with a signal, but PCI_DEVSEL* does not follow with a signal to allow the cycle to complete. To prevent PCI_TRDY PCI_STOP this, the core provides the programmable timer to determine the point at TRDY_TIMEOUT which the Master will abandon the cycle.

  • Page 159: Table 8-21 Configuration Pci

    Chapter 8: PCI/G-Bus Bridge 8.7 Configuration Register Descriptions 8.7.1 PCI Vendor ID Register Address: 00h Bits Used: Bits 15:0 are used at this address. Access: Read-Only Table 8-21 Configuration PCI Vendor ID Register Bit(s) Description Reset 15:0 Manufacturer ID 0x102F 8.7.2 PCI Device ID Register Address: 00h Bits Used: Bits 31:16 are used at this address.

  • Page 160: Table 8-24 Configuration Pci S

    Chapter 8: PCI/G-Bus Bridge 8.7.4 PCI Status Register Address: 04h Bits Used: Bits 31:16 are used at this address. Access: Read Only, Status (Status bits: see PCI 2.1 Specifications for usage) Reports the status of operations on the PCI bus. Also indicates the * timing that DEVSEL has been selected.

  • Page 161: Table 8-26 Configuration Class

    Chapter 8: PCI/G-Bus Bridge 8.7.6 Class Code Register Address: 08h Bits Used: Bits 31:8 are used at this address. Access: Read Only The Class Code register contains a code value identifying the generic function of this device. Table 8-26 Configuration Class Code Register Bits Description Reset...

  • Page 162: Table 8-28 Configurationm

    Chapter 8: PCI/G-Bus Bridge 8.7.8 Master Latency Timer Register Address: 0Ch Bits Used: Bits 15:8 are used at this address. Access: Read/Write The Master Latency Time Register is an 8-bit register controlling the amount of time that the core, as a bus Master, can perform burst transfers if another Master requests the bus. The two least significant bits are hardwired to “0”, allowing interval changes in increments of four clocks.

  • Page 163: Table 8-31 Subsystem Id R

    Chapter 8: PCI/G-Bus Bridge 8.7.11 Subsystem ID Register Address: 2Ch Bits Used: 31:16 are used at this address. Access: Read-Only Subsystem ID is defined in section 6.2.4 of the PCI 2.1 Specifications. Table 8-31 Subsystem ID Register Bits Description Reset 15:0 Subsystem ID 0000h...

  • Page 164: Table 8-36 Configuration

    Chapter 8: PCI/G-Bus Bridge 8.7.14 MIN_GNT Register Address: 3Ch Bits Used: Bits 23:16 are used at this address. Access: Read/Write Table 8-34 MIN_GNT Register Bits Description Reset Identifies length of burst period, assuming a 33 MHz clock. Is in units of 0.25 µS.

  • Page 165: Table 8-37 Configuration Retry

    Chapter 8: PCI/G-Bus Bridge 8.7.17 Retry Timeout Value Address: 40h Bits Used: Bits 15:8 are used at this address. Access: Read/Write Table 8-37 Configuration Retry Timeout Value Bits Description Reset Sets number of retries that the core will perform as Master.

  • Page 166: Chapter 9. Dma Controller

    Chapter 9: DMA Controller 9. DMA Controller The Direct Memory Access Controller (DMAC) employed in the TX7901 is a flexible direct memory access engine that optimizes the data transfers between the C790 bus and the G- Bus without significant intervention of the core CPU. Instead of having the CPU read data from one source and write it to another, the DMA controllers can be programmed to automatically transfer data independent of the CPU.

  • Page 167: M Odes Of O Peration

    Chapter 9: DMA Controller 9.1 Modes of Operation The DMAC has eight independent channels. As channels become active, the Arbiter grants control to the highest priority channel. The DMAC then begins reading the source data from the source address and puts the data into the FIFO queue. When the data are ready in the FIFO queue, the DMAC transfers the data out to the destination address.

  • Page 168: Figure 9-1 Round -Robin Priority

    Chapter 9: DMA Controller DMA2 DMA1 DMA3 DMA0 DMA4 DMA7 DMA5 DMA6 Figure 9-1 Round-Robin Priority Scheme 9.1.2 Source and Destination The DMAC conducts data transfers within memory or between a memory and an I/O device. The device at the data transfer origin is called a source device, and the device at the data transfer destination is called a destination device.

  • Page 169: Table 9-1 Block And Slicet

    Chapter 9: DMA Controller Table 9-1 shows the types of transfer that can be performed in block mode. Table 9-1 Block and Slice Transfer Types Block Mode Slice Mode • Memory to I/O • Memory to I/O • I/O to Memory •...
  • Page 170 Chapter 9: DMA Controller For example, Figure 9-2 illustrates a situation in which DMA channel 5 is programmed in the slice mode, and it requires two slice transfers or five DMA bus cycles to finish the data transfer. SLICE #1 SLICE #2 DMA Bus DMA Bus...

  • Page 171: Chain Mode

    Chapter 9: DMA Controller 9.1.6 Chain Mode In the Chain mode, the DMA Descriptor list located in the local main memory contains all the necessary information for each DMA transfer. Each Descriptor consists of a Source Address, Destination Address, Byte Count, and Next Record Pointer. The Descriptor must be aligned to a 16-byte boundary.

  • Page 172: Bit G-Bus I/O

    Chapter 9: DMA Controller 9.1.9 32-/64-bit G-Bus I/O The DMAC supports 32-/64-bit G-Bus I/O using dynamic bus sizing. When the DMAC initiates a G-Bus cycle, the I/O device communicates its device size through gAck32B and gAck64B. For 32-bit devices, the DMAC reads or writes data on the lower 32 bits of the G-Bus only. 9.1.10 Memory Byte Alignment Support If the C790 bus memory start address is not quad-word aligned, the DMAC divides the...

  • Page 173: Restarting A Disabled Channel

    Chapter 9: DMA Controller Arbiter Destination Source Address Address 8 DMA Channels Source Device Data Data FIFO Data Byte Count Destination Device 0x1000 Source Address 0x1004 Destination Address 0x1008 Next Record Pointer, 0X2000 0x100C Transfer #1 Byte Count 0x2000 Source Address 0x2004 Destination Address 0x2008...

  • Page 174: R Egisters

    Chapter 9: DMA Controller 9.2 Registers Table 9-2 is a summary of all the DMAC registers. The DMAC registers reside on the G-Bus interface. Any G-Bus master can program the DMAC registers using G-Bus single read or write cycles. All DMAC registers are 64 bits wide and byte addressable. Table 9-2 DMAC Registers Register Address...

  • Page 175: Channel Control Registers (Ccr0 - Ccr7)

    Chapter 9: DMA Controller Register Address Register Name Symbol 0x1E00_1500 CCR5 Channel 5 Control Register 0x1E00_1510 CSR5 Channel 5 Status Register 0x1E00_1520 SAR5 Channel 5 Source Address Register 0x1E00_1530 DAR5 Channel 5 Destination Address Register 0x1E00_1540 BCR5 Channel 5 Byte Count Register 0x1E00_1550 NRPR5 Channel 5 Next Record Pointer Register...

  • Page 176: Table 9-3 Channel Controlr

    Chapter 9: DMA Controller Table 9-3 Channel Control Register Field Descriptions Bit(s) Field Default Description 63:25 – Reserved (0) DMA Channel Enable (0) This bit enables this DMA channel. 0 - Disable the DMA channel. 1 - Enable the DMA channel. DMA Channel Start (0) This bit is reset automatically once the DMA channel is granted in normal mode or upon the transfer completion of the entire block of data in the chain...
  • Page 177 Chapter 9: DMA Controller Bit(s) Field Default Description 101 - 6 quad-words 110 - 7 quad-words 111 - 8 quad-words Chain Mode (0) This bit indicates the Chain mode when it is set. The Chain mode only works in conjunction with the Block mode. This bit indicates the Normal mode when it is reset.

  • Page 178: Table 9-4 Channel Statusr

    Chapter 9: DMA Controller Bit(s) Field Default Description 01 - Reserved 10 - Increment (memory device) 11 - Decrement (memory device) Note: If SCM = 10, then DCM must not be 11. If SCM = 11, then DCM must not be 10. 9.2.2 Channel Status Register (CSR0 –...

  • Page 179: Table 9-5 Source Addressr

    Chapter 9: DMA Controller Bit(s) Field Default Description 0: The interrupt bit is cleared. 1: The interrupt bit is ignored. G-Bus Error Interrupt If there is a G-Bus error interrupt, the DMAC will finish the pending DMA transfer and stay idle until the G-Bus error interrupt is cleared. In this state, the DMAC will stay idle even if the G-Bus error interrupt is masked (GBIE=0).

  • Page 180: Table 9-6 Destination Address

    Chapter 9: DMA Controller 9.2.4 Destination Address Register (DAR0 - DAR7) These eight registers contain the destination address of the DMA operation in progress for each of the eight DMA channels. DA[31:0] Table 9-6 Destination Address Register Field Definitions Bit(s) Field Default Description...

  • Page 181: Table 9-8 Next Record Pointer

    Chapter 9: DMA Controller 9.2.6 Next Record Pointer Registers (NRPR0 – NRPR7) These eight registers contain the address of the next record in the Descriptor list. These registers are only used when the DMA channel is configured in the Chained mode. A Null value for a register indicates the last Descriptor in the list.

  • Page 182: C790 Bus Error Address Register (Cbeaddr)

    Chapter 9: DMA Controller Bit(s) Field Default Description DMA Global Chain Mode Completion Interrupt GCCI 0: No Chain Mode completion interrupt in any DMA channel 1: Chain Mode completion interrupt in some DMA channels DMA Global C790 Bus Error Interrupt GCBI 0: No C790 bus error interrupt in any DMA channel 1: C790 bus error interrupt in some DMA channels...

  • Page 183: Table 9-11 G-Bus Error Address

    Chapter 9: DMA Controller 9.2.9 G-Bus Error Address Register (GBEADDR) GBEA[31:0] Table 9-11 lists the fields of the G-Bus Error Address Register. Table 9-11 G-Bus Error Address Register Field Descriptions Bit(s) Field Default Description 63:32 – Reserved G-Bus Error Address When the DMAC is the master on the G-Bus and encounters a 31:0 GBEA...

  • Page 184: Table 10-1 Timer Modes Andc

    Chapter 10: Programmable Timer/Contents 10. Programmable Timer/Counters 10.1 Features The TX7901 Programmable Timer/Counters consist of three timer “channels”, Timer 0, Timer 1, and Timer 2. Timer 0 operates only in the Interval Timer Mode. Timer 1 is capable of operating only in the Interval Timer and Pulse Generation Modes. Timer 2 is capable of operating in the Interval Timer, Pulse Generator, and Watchdog Timer Modes.

  • Page 185: Figure 10-1 Timer Modulec

    Chapter 10: Programmable Timer/Contents 10.2 Block Diagrams Figure 10-1 shows the block diagram for the programmable Timer/Counters and their connections inside the TX7901. This is followed in Figure 10-2 by a block diagram of the internal connections within a maximally equipped timer such as Timer 2. The internal connections within Timer 0 and Timer 1 are similar to Timer 2 except for each of them lacking some features present in Timer 2.

  • Page 186: Figure 10-2 Timer 0, Timer

    Chapter 10: Programmable Timer/Contents TX7901 G-Bus Timer 0 Timer 1 TIMIN1 External Timer 2 Clock Register TIMIN2 Inputs r/w Control Logic Timer Read Clock Register Clock TX7901 Source Clock CLEAR Internal Divider Select Frequency 24-bit Counter Clock ×1/2 to Select ×1/256 Compare Compare...

  • Page 187: S Ignals

    Chapter 10: Programmable Timer/Contents 10.3 Signals Table 10-2 lists the signals that implement the interface between the Timer/Counter and the C790. Direct inputs and outputs to the outside of the TX7901 are in the upper case. Table 10-2 TX7901 Programmable Timer/Counter Signals Signal Name Description gbsBusClk...

  • Page 188: Table 10-3 Timer /Counterc

    Chapter 10: Programmable Timer/Contents Signal Name Description output is connected to Interrupt 6 of the Interrupt Controller. This output will be asserted when the Max Count is reached, and will remain asserted until the proper registers are written to (to de-assert it), or until the C790 is Reset. Active Low output for Timer 1 when it is configured as a Periodic Interval Timer.

  • Page 189: Table 10-4 Field Descriptions For Table 10-5 Fields Descriptions Of

    Chapter 10: Programmable Timer/Contents 10.4.1 Timer Control Registers TMTCR0, TMTCR1, TMTCR2 The following figure and Table 10-4 detail the fields of Timer Control Registers TMTCR0, TMTCR1, and TMTCR2. Table 10-4 Field Descriptions for Timer Control Registers TMTCRx Bit(s) Field Field Name Description 31:8 –...

  • Page 190: Interval Timer Mode Registers Tmitmr0, Tmitmr1, Tmitmr2

    Chapter 10: Programmable Timer/Contents 10.4.2 Interval Timer Mode Registers TMITMR0, TMITMR1, TMITMR2 The following figure and Table 10-5 detail the fields for the Interval Timer Registers TMITMR0, TMITMR1, and TMITMR2. Table 10-5 Fields Descriptions of Interval Timer Mode Registers TMITMRx Bit(s) Field Field Name...

  • Page 191: Table 10-6 Field Descriptions For Table 10-7 Field Descriptions For

    Chapter 10: Programmable Timer/Contents 10.4.3 Divider Registers TMCCDR0, TMCCDR1, TMCCDR2 The following figure and Table 10-6 detail the fields of the Divider Registers, TMCCDR0, TMCCDR1 and TMCCDR2. Table 10-6 Field Descriptions for Divider Registers TMCCDR0, TMCCDR1, TMCCDR2 Bit(s) Field Field Name Description 31:3 –...

  • Page 192: Pulse Generator Mode Registers Tmpgmr1, Tmpgmr2

    Chapter 10: Programmable Timer/Contents 10.4.4 Pulse Generator Mode Registers TMPGMR1, TMPGMR2 The following figure and Table 10-7 detail the fields of the Pulse Generator Mode Registers for Timers 1 and 2, TMPGMR1 and TMPGMR2. Table 10-7 Field Descriptions for Pulse Generator Mode Registers TMPGMRx Field Field Name Description...

  • Page 193: Table 10-8 Watchdog Timerm

    Chapter 10: Programmable Timer/Contents 10.4.5 Watchdog Timer Mode Register (TMWTMR) Fields The following figure and Table 10-8 detail the fields of the Watchdog Timer Mode Register, TMWTMR. Table 10-8 Watchdog Timer Mode Register (TMWTMR) Field Descriptions Bit(s) Field Field Name Description 31:17 –...

  • Page 194: Table 10-9 Field Descriptions For Table 10-10 Field Descriptions For

    Chapter 10: Programmable Timer/Contents 10.4.6 Timer Interrupt Status Registers TMTISR0, TMTISR1, TMTISR2 The following figure and Table 10-9 detail the fields of the Timer Interrupt Status Registers, TMTISR0, TMTISR1, and TMTISR2. Note that Timers 0 and 1 use only some of these fields. Table 10-9 Field Descriptions for Timer Interrupt Status Registers TMTISRx Field Field Name...
  • Page 195 Chapter 10: Programmable Timer/Contents Field Field Name Timer(s) Description When the Interval Timer Interrupt is enabled by setting the TIIE bit in the Interval Timer Mode Register (TMITMRx) and the counter value matches the compare register TMCPRA value during counting, the TIIS bit is set, asserting the TMINTREQ* line Low.

  • Page 196: Fields For Timer Compare Registers A (Tmcprax) And B (Tmcprbx)

    Chapter 10: Programmable Timer/Contents 10.4.7 Fields for Timer Compare Registers A (TMCPRAx) and B (TMCPRBx) The following figure and Table 10-10 detail the fields of the Timer Compare Registers TMCPRAx and TMCPRBx. Timer Compare Register A TCVA TCVA Timer Compare Register B TCVB TCVB Table 10-10 Field Descriptions for Time Compare Registers TMCPRAx, TMCPRBx...

  • Page 197: Table 10-11 Field Descriptions Of

    Chapter 10: Programmable Timer/Contents 10.4.8 Timer Read Registers (TMTRR0, TMTRR1, TMTRR2) The following figure and Table 10-11 detail the fields of the Timer Read Registers TMTRR0, TMTRR1 and TMTRR2. TCNT TCNT Table 10-11 Field Descriptions of Timer Read Registers TMTRRx Bit(s) Field Field Name...

  • Page 198: Table 10-12 Interrupt Control With The Table 10-13 Divider Values And

    Chapter 10: Programmable Timer/Contents (TMITMR) is set to “1”. When the TIIE bit is subsequently cleared to “0”, this causes the interrupt logic to mask the inverted TIIS bit (and to not transmit it), effectively disabling the interrupt request signal TMINTREQ*. When the Timer Interval Interrupt status (TIIS) bit of the status register (TMTISR) is cleared to “0”...

  • Page 199: Figure 10-3 Interval Timero

    Chapter 10: Programmable Timer/Contents Count Value Counter halted, Zero clear Zero clear but not reset disabled Counter reset enabled enabled TMCPRA Counter disabled Compare Value Counter Enabled Counter reset 0x000000 disabled Time changes TMODE= CCS= TCE= CRE= TZCE= TIIE= TMINTREQ* Timer interrupt TIIS = 0...
  • Page 200 Chapter 10: Programmable Timer/Contents 10.5.1.1 Divisors For Counting Table 10-13 shows the counter frequencies that result from selecting and dividing the internal 66/50 MHz clock by the decimal Divider values given (using these values in the Divider Register). These frequencies are used in all three counter modes. Table 10-13 Divider values and Counter Frequencies Generated 66.7 MHz Divider...

  • Page 201: Pulse Generator Mode Operation

    Chapter 10: Programmable Timer/Contents 10.5.2 Pulse Generator Mode Operation This mode is set up by setting the timer mode (TMODE) field of the Timer Control Register (TMTCR) to 0b01 (binary). In this mode, rectangular pulses of specific frequency and duty-cycle can be generated with the help of the two compare registers TMCPRA and TMCPRB.

  • Page 202: Figure 10-5 Pulse Generator

    Chapter 10: Programmable Timer/Contents Count Value TMCPRB Compare Value TMCPRA Compare Value 0x000000 Time TMODE = 01 TIIE TCE = 0 TCE = 1 TMFFOUT Figure 10-5 Pulse Generator Mode Operation TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) 10-19...

  • Page 203: Figure 10-6 Watchdog Timer

    Chapter 10: Programmable Timer/Contents 10.5.3 Watchdog Timer Mode Operation This mode is set up by setting the timer mode (TMODE) field of the Timer Control Register (TMTCR) to 0b10 (binary). In this mode, when the Timer/Counter Enable (TCE) bit of the TMTCR register is set to “1”, the 24-bit counter begins counting.

  • Page 204: Figure 10-7 Interval Timinge

    Chapter 10: Programmable Timer/Contents 10.5.4 Examples of Timer/Counter Timing These examples illustrate the different modes of operation of the various timers. (Refer to Section 10.1 at the beginning of the chapter for details.) 10.5.4.1 Interval Timer Mode Interrupt Timing Figure 10-7 illustrates a case in which Timer Compare Value A (TCVA) is “3”, and the timer input clock is the 50 MHz internal G-Bus Clock.

  • Page 205: Figure 10-9 Pulse Generator

    Chapter 10: Programmable Timer/Contents Pulse Generator Mode Flip-Flop Output Timing Figure 10-9 illustrates a case in which Timer Compare Value A (TCVA) is “1” and Timer Compare Value B (TCVB) is “3”, in the Pulse Generator Timing Mode. The Initial value for the Timer Flip-flop is 0, and the Timer Flip-Flop is initialized simultaneously with TMPGMR being written to.

  • Page 206: Table 11-1 Maskable Interrupt

    Chapter 11: Interrupt Controller 11. Interrupt Controller 11.1 Introduction The Interrupt Controller arbitrates all the interrupt requests from internal and external devices and sends the interrupt request that was granted access to the processor. The interrupt controller features are: 32 internal and external interrupt requests Interrupt mask Level trigger only 11.2 Operation...

  • Page 207: Table 11-2 Interrupt Controller

    Chapter 11: Interrupt Controller Interrupt Number Interrupt Source External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 PCI0 Reset PCI1 Reset 22:31 Reserved Once the C790 detects the interrupt request, it reads from the interrupt status register and mask register and determines which interrupt it should service.

  • Page 208: Table 11-4 Interrupt Maskr

    Chapter 11: Interrupt Controller 11.3.2 Interrupt Mask Register (IRMASK) The Interrupt Mask Register enables interrupts to be selectively masked from causing an interrupt to the C790. The following figure and Table 11-4 detail the fields of the Interrupt Mask Register. IRMASK[31:16] IRMASK[15:0] Table 11-4 Interrupt Mask Register Field Description...

  • Page 209: O Verview

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12. 10/100 IEEE802.3 Media Access Controller 12.1 Overview This chapter describes a 64-bit G-Bus Media Access Controller (MAC) for the TX7901. It operates at data transfer rates of 100 Mbps or 10 Mbps. In the half-duplex mode, the controller implements the IEEE 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol.

  • Page 210: C790 And Mac Dma

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.1.1 C790 and MAC DMA The MAC provides a powerful host system interface through its own DMA. It manages the shared memory structures automatically through the frame Descriptors and buffers. Shared Memory TxFrm Buffer 0 Descriptor 0 Buffer 1...

  • Page 211: Mac And Mii

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.1.2 MAC and MII The MAC consists of a transmit block, a receive block, a flow control block, a set of control and status registers, counters and a serial controller for the MII (Media Independent Interface) station management interface.

  • Page 212: Mii (M Edium I Ndependent I Nterface )

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.2 MII (Medium Independent Interface) Table 12-1 lists the Medium Independent Interface Signals. Table 12-1 MII Interface Signals Input / Signal Description Output Transmit Clock. Provides the timing reference for the transfer macxTxClk Input of the macxTxEn, macxTxD, and macxTxEr to the PHY.

  • Page 213: Mac R Egisters And C Ounters

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3 MAC Registers and Counters Each of the two MACs available in the TX7901 occupies a 4 KB block of address space on the G-Bus for its internal structures. The base addresses of the corresponding blocks for MAC 0 and MAC 1 are 0x1E00_5000 and 0x1E00_6000 respectively.
  • Page 214 Chapter 12: 10/100 IEEE802.3 Media Access Controller Offset Register Width R / W Description Notes 0x118 NBTBReg [63:0] Non Back-to-Back IPG gap 0x120 peCLRT [63:0] Internal Test Register (peCLRT) 0x128 peMAXF [63:0] Internal Test Register (peMAXF) 0x130 pePNCT [63:0] Internal Test Register (pePNCT) 0x138 peTBCT [63:0]...

  • Page 215: Table 12-4 Miim

    Chapter 12: 10/100 IEEE802.3 Media Access Controller Table 12-4 MIIM (Media Independent Interface Management) Registers Offset Width R / W Register Note 0x400H [63:0] MIIM Control Register 0x 408H [63:0] MIIM Data Register Table 12-5 MAC “Perfect Table” Values Offset Width R / W Register...

  • Page 216: Register Functionality And Field Descriptions

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.1 Register Functionality and Field Descriptions MAC Registers are used primarily for configuration and error notification. The MAC also has diagnostic registers that are typically used for system diagnostic testing. Configuration registers are only written to at system start-up, or whenever the chip is reset. They should not be updated while the MAC is transmitting or receiving frames.
  • Page 217 Chapter 12: 10/100 IEEE802.3 Media Access Controller Bit(s) Field Description Programmable Burst Length (011) Indicates the maximum number of 8-byte values to be transferred in one DMA transaction. X00 2 (16 bytes) X01 4 (32 bytes) X10 8 (64 bytes) X11 16 (128 bytes) It is also a kind of count threshold, and has different definitions in the TxFIFO and the RxFIFO.
  • Page 218 Chapter 12: 10/100 IEEE802.3 Media Access Controller Bit(s) Field Description the PHY. When TxSQE is 1, the transmitter reports the status of SQE test. This bit should be 0 if the 100Base-X or 100Base-T PHY being used does not perform the SQE test.
  • Page 219 Chapter 12: 10/100 IEEE802.3 Media Access Controller Bit(s) Field Description to change. Transmit Start (0) This bit works with TxEnable. If TxEnable is 0, TxStart is ignored. When set, the MAC enters a running state. It will poll the Descriptor first, and then transmit frames. When TxStart cleared, it will stop the transmission.
  • Page 220 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.1.3 Receive Frame Configuration Register (RFCReg) The Receive Frame Configuration register defines the rules for frame reception on MAC. These can be changed to accommodate different options. Upon the completion of reset, this register’s default value is 0x2008_0000.
  • Page 221 Chapter 12: 10/100 IEEE802.3 Media Access Controller Bit(s) Field Description is reset, the MAC will not self-initiate any flow control algorithms. Strip CRC (0) RxNoCRC When set, the MAC strips the CRC (the last 4 bytes) from all frames being received. Reject Frame MII Receive Error (0) RxErr See note below.
  • Page 222 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.1.4 Transmit Status Register (TSReg) The Transmit Status register is updated after a frame is fully transmitted or the transmission of a frame is aborted due to an error. The register can be read to determine if the frame was successfully transmitted or to determine what errors occurred.
  • Page 223 Chapter 12: 10/100 IEEE802.3 Media Access Controller Bit(s) Field Description When set, indicates that a transmission was aborted due to a collision occurring later than 512 bit times. Loss of Carrier (0) TxLCar When set, indicates the macxCRS input was low during the transmission of a frame. Signal Quality Error Missed (0) When set, indicates that the SQE test on the macxCOL signal line was not detected at the end of a transmission.
  • Page 224 Chapter 12: 10/100 IEEE802.3 Media Access Controller Table 12-12 RSReg Register Field Descriptions Bit(s) Field Description Fatal Bus Error (0) RxFBE When set, indicates that a bus error occurred, then the MAC disables all of its bus access operations. Receive Process State (000) 000 : Idle, RxEnable is 0 001 : Waiting, there are no frame data in RxFIFO, or data is less than the RxSOFTh (in RCReg) 010 : Waiting, there are no data in RxFIFO, or data is less than the RxSOFTh and there is no...
  • Page 225 Chapter 12: 10/100 IEEE802.3 Media Access Controller Bit(s) Field Description When set, indicates that the destination address of the received frame is a physical address. Multicast Address (0) RxMA When set, indicates that the destination address of the received frame is a multicast address. Broadcast Address (0) RxBA When set, indicates that the destination address of the received frame is a broadcast address.
  • Page 226 Chapter 12: 10/100 IEEE802.3 Media Access Controller Bit(s) Field Description TxCPauseM MAC Pause Frames Transmitted Counter Overflow Mask (0) TxCGt1KM Frames Transmitted (1024~max byte) Counter Overflow Mask (0) TxC1KM Frames Transmitted (512~1023 byte) Counter Overflow Mask (0) TxC511M Frames Transmitted (256~511 byte) Counter Overflow Mask (0) TxC255M Frames Transmitted (128~255 byte) Counter Overflow Mask (0) TxC127M...
  • Page 227 Chapter 12: 10/100 IEEE802.3 Media Access Controller Bit(s) Field Description TxC511 Frames Transmitted (256~511 byte) Counter Overflow (0) TxC255 Frames Transmitted (128~255 byte) Counter Overflow (0) TxC127 Frames Transmitted (65~127 byte) Counter Overflow (0) TxC64 Frames Transmitted (64 byte) Counter Overflow (0) TxCBC Broadcast Frames Transmitted Counter Overflow (0) TxCMC...
  • Page 228 Chapter 12: 10/100 IEEE802.3 Media Access Controller Bit(s) Field Description RxC511M Frames Received (256~511 byte) Counter Overflow Mask (0) RxC255M Frames Received (128~255 byte) Counter Overflow Mask (0) RxC127M Frames Received (65~127 byte) Counter Overflow Mask (0) RxC64M Frames Received (64 byte) Counter Overflow Mask (0) RxCBCM Broadcast Frames Received Counter Overflow Mask (0) RxCMCM...
  • Page 229 Chapter 12: 10/100 IEEE802.3 Media Access Controller Bit(s) Field Description RxCBC Broadcast Frames Received Counter Overflow (0) RxCMC Multicast Frames Received Counter Overflow (0) RxCFrm Readable Frames Received Counter Overflow (0) RxCByte Total Byte Received Counter Overflow (0) 12.3.1.10 LSAReg I, II, Local Station Address I & II Registers These address registers are used by the MAC when transmitting MAC control frames.
  • Page 230 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.1.11 Bus Error Address Register (BusErrReg) The Bus Error Address Register saves the G-Bus Address when a Bus Error occurs while the MAC is the G-Bus Master. Upon the completion of reset, this register’s default value is 0x0000_0000.
  • Page 231 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.1.13 VLAN Tag Register (VLANReg) When frames are transmitted or received, the 13th and 14th byte in the frame are compared to this register to determine if the frame is tagged with a one-level VLAN ID or a two-level VLAN ID.
  • Page 232 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.1.15 Receive Frame Descriptor Pointer Register (RDPReg) The Receive Frame Descriptor Pointer Register contains the address of the first frame Descriptor for reception. The system must set this register to a properly initialized frame Descriptor before enabling reception.
  • Page 233 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.1.17 Transmit frame Current Descriptor Pointer Register (TCDReg) The Transmit frame Current Descriptor Pointer Register contains the address of the current Descriptor used for transmission. When the MAC Tx is stopped or suspended (i.e. TFCReg[TxStart] = 0), this register shows the Descriptor where the error occurred or where something is not available.
  • Page 234 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.1.19 Back to Back IPG Register (IPGReg) This Register contains the first bus error address. IPGT Table 12-27 IPGReg Register Field Descriptions Bits Field Description 63:7 – Reserved (0x000) IPGT Back-To-Back IPG length. Default is 0x15. Inter-Packet Gap (IPG) is the measurement between the last nibble of CRC and the first nibble of the preamble of the next packet.
  • Page 235 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.1.20 Non Back-To-Back IPG Register (NBTBReg) This Register contains the programmable transmit IPG for non back-to-back transmits. This register default value is 0x0012. IPGR1 IPGR2 Table 12-29 NBTBReg Register Field Descriptions Bit(s) Field Description 63:15 –...

  • Page 236: Counters

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.2 Counters The MAC provides an extensive list of network event counters. The counters are cleared to zero upon a hardware reset or software reset (CntRst – see Table 12-7). The counters will count all events even when the port is disabled or the RxFIFO overflows.
  • Page 237 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.2.9 Frames Transmitted (TxFrame1K) This 32-bit counter counts the successfully transmitted frames that are between 512 and 1023 bytes (both inclusive) in length (including the CRC). 12.3.2.10 Frames Transmitted (TxFrameGt1K) This 32-bit counter counts the successfully transmitted frames that are greater than or equal to 1024 bytes and less than or equal to the maximum size.
  • Page 238 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.2.19 Transmit Underflow Errors This 32-bit counter counts the number of TxFIFOs that underflowed. 12.3.2.20 Total Bytes Received This 32-bit counter counts all received bytes. This includes CRC bytes and bytes from erroneous frames. 12.3.2.21 Total Readable Frames Received This 32-bit counter counts the good frames received.
  • Page 239 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.2.29 Frames Received (RxFrameGt1K) This 32-bit counter counts the successfully received frames that are greater than or equal to 1024 bytes and less than or equal to the maximum size. The upper valid frame size can be set to 1518, 1522, or 1538 bytes.
  • Page 240 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.2.38 No RxFIFO Missed Frames This 32-bit counter counts the frames that are not able to be stored in the RxFIFO, which has overflowed. 12.3.2.39 No RxDescriptor Missed Frames This 32-bit counter counts the frames that are not able to be stored in the RxFIFO since there is no receive Descriptor.

  • Page 241: Figure 12-3 Fields Of Miim C

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.3 MIIM (Media Independent Interface Management) 12.3.3.1 MIIM Control Register The MIIM control register allows the C790 to read and write any one of the PHYs connected to the MAC. This register provides bits to address a particular PHY, to address a register, to set the read or write direction, and to indicate that the read or write is still in progress.

  • Page 242: Figure 12-4 Fields Of Miim D

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.3.2 MIIM Data Register The MIIM data register is used in conjunction with the MIIM control register. When reading a PHY register, data are written to this register by the PHY. When writing to a PHY register, data from this register are written to the PHY.
  • Page 243 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.4.1 Perfect Table The Perfect Table holds 16 destination addresses (full 48-bit MAC addresses). The MAC compares the addresses of any incoming frame to these addresses, and also checks the status of the Receive Frame Configuration Register. It rejects addresses that: Do not match if inverse filtering is reset.

  • Page 244: Fifo Addresses

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.3.5 FIFO Addresses The FIFO address space is for debugging purposes. It allows the C790 to read or write to the FIFO. This may be done only in the FIFO diagnostic mode. TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) 12-36...

  • Page 245: Figure 12-6 Descriptor Ring And Figure 12-7 Receive Descriptor

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.4 Memory Organization (Frame Descriptor) This section describes the organization of the MAC Frame Descriptor in memory. 12.4.1 Descriptor Lists and Data Buffers The MAC transfers frame data between the C790 memory and the FIFO using a Descriptor list.

  • Page 246: Receive Descriptors

    Chapter 12: 10/100 IEEE802.3 Media Access Controller The buffer address must be 8-byte aligned while the Descriptor address must be 16-byte aligned. 12.4.2 Receive Descriptors The format of the Receive Descriptors is shown below. It is made of two double-words, and the fields are described in more detail in Table 12-34.
  • Page 247 Chapter 12: 10/100 IEEE802.3 Media Access Controller Word 0 Fields Bit(s) Field Description [1:0] Ethernet type IEEE type VLAN I VLAN II Descriptor Error When set, indicates that a frame truncation was caused by a frame that does not fit within RxBufErr the current Descriptor buffers, and that the MAC does not own the next Descriptor.

  • Page 248: Figure 12-8 Transmit Descriptor

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.4.3 Transmit Descriptors The format of the Transmit Descriptors is shown below. It is made of two doublewords, and the fields are described in more detail in Table 12-35. Byte-Count Buffer 1 Byte-Count Buffer 2 Control Bits Status Bits Buffer Address 1...
  • Page 249 Chapter 12: 10/100 IEEE802.3 Media Access Controller Word 0 Fields Bit(s) Field Description full-duplex. Deferred When set, indicates the frame transmission was delayed because of a deferral. This bit is TxDefer set when a frame is transmitted with a collision and the standard backoff is selected in the configuration register.

  • Page 250: F Unctional D Escription

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.5 Functional Description 12.5.1 The MAC provides a master DMA interface that is capable of reading or writing data at high speed. When the MAC wants to transfer data to/from memory, it follows the 64-bit G-Bus conventions.
  • Page 251 Chapter 12: 10/100 IEEE802.3 Media Access Controller EOF cleared, it indicates an intermediary buffer, and the transmit process attempts to acquire the next Descriptor. If the EOF is set, it indicates the last buffer of the frame. After the last buffer of the frame has been transmitted to MII, the MAC writes back the final status information to the transmit Descriptor.
  • Page 252 Chapter 12: 10/100 IEEE802.3 Media Access Controller before the frame ends. • When the MAC completes the reception of a frame and the current received Descriptor has been closed • When the receive process is suspended because of a host-owned buffer, and a new frame is received.

  • Page 253: Fifo Operation

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.5.2 FIFO Operation FIFOs are used internally to buffer frames before they are transmitted on the network or before they are put to memory. The TxFIFO (1 KB) is deep enough to support the retransmission of a frame if a collision occurs within the first 512 bit times of transmission.
  • Page 254 Chapter 12: 10/100 IEEE802.3 Media Access Controller This time the loop goes deeper than the previous case, including the MAC block. Status bits and counters are all active. To do a loop back test, the MAC should be set in the full-duplex mode. 12.5.2.3 TxFIFO Specific Function The TxFIFO provides the mechanism for sending frame data through the MAC and onto the network.
  • Page 255 Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.5.2.3.5 Error Conditions The TxFIFO has the capability of stopping its operation when an error occurs. This option can be enabled by setting the TxEnHalt bit in the transmit frame configuration register. The following conditions cause the TxFIFO to stop: excessive deferral, excessive collisions, late collision, or TxFIFO overrun.
  • Page 256 Chapter 12: 10/100 IEEE802.3 Media Access Controller register are put in the frame Descriptor after each frame datum has been transferred into memory. Second, event counters are updated based on the status at the end of a receive frame. These counters can be read at any time. 12.5.2.4.5 Undersized and Fragment Rejection A frame is received that is less than 64 bytes and has a good CRC (undersized), has a bad...

  • Page 257: Mii Interface

    Chapter 12: 10/100 IEEE802.3 Media Access Controller 12.5.3 MII Interface The MII interface is described in this section. 12.5.3.1 macxTxClk TXCLK is the transmit clock used to provide the timing reference for the transfer of the macxTxEn, macxTxD[3:0] and macTxEr to the PHY. The MAC handles internal synchronization between gbsBusClk and these transmit signals.
  • Page 258 Chapter 12: 10/100 IEEE802.3 Media Access Controller • FIFO control is returned to its idle configuration. Any frame being transmitted or received at the time of reset is lost. To clear all counters gresetB should keep at least 40 gbsBusClk. 12.5.5.2 Software Reset There are four different reset bits in the CCReg (Command and Configuration Register).
  • Page 259 Chapter 13: Removed 13. Removed TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) 13-1...
  • Page 260 Chapter 13: Removed TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) 13-2...

  • Page 261: O Verview

    Chapter 14: UARTS WITH FIFOS 14. UARTS WITH FIFOS 14.1 Overview The TX7901 has two individual UARTs (hereinafter referred to as simply “The UARTs”), high-performance universal asynchronous receiver/transmitters each having two 16-byte FIFOs – one for transmit and one for receive. Each of the UARTs also includes a 16-byte programmable baud rate generator, an 8-bit scratch register, and eight modem control lines.

  • Page 262: Key Features

    Chapter 14: UARTS WITH FIFOS 14.1.1 Key Features Software-compatible with NSC NS16550A Programmable word length, stop bits, and parity Programmable baud rate generator Interrupt generator Diagnostic loop-back mode Scratch register Two 16-byte FIFOs Scan test ready 14.1.2 Introduction The UARTs are universal asynchronous receiver/transmitters that are fully programmable through the G-Bus Interface.

  • Page 263: Receive Operation

    Chapter 14: UARTS WITH FIFOS 14.2.2 Receive Operation Data are sampled into the RX Shift Register using RCLK. A filter is used to remove spurious inputs that last for less than two clock periods. When the complete word has been clocked into the receiver, the data bits are transferred to the RX Buffer Register or to the RX FIFO (if enabled) to be read by the G-Bus.

  • Page 264: Uart D Evice R Egister D Escription

    Chapter 14: UARTS WITH FIFOS SIGNAL TYPE DESCRIPTION gbsgLastB Input The G-Bus Master asserts this signal to indicate the last transaction. G-Bus Acknowledge. UART asserts this signal to acknowledge a 32-bit width urtgAck32B Output read/write transfer. urtgData[63:0] Output 64-bit read data from UART to G-Bus Serial Interface (Two sets) Receive/Transmit clock, derived from CLK.
  • Page 265 Chapter 14: UARTS WITH FIFOS Table 14-2 Device Register Addressing for UARTs 0 & 1: Little Endian Mode G-Bus Register Bank Notes Address Byte Offset Offset Acronym Name [7:2] Enables 0000_00 1110 Receive Buffer Register R/O. See 14.4.2. 0000_00 1110 Transmit Holding Register W/O.

  • Page 266: Receive Buffer Register (Rbr0, Rbr1)

    Chapter 14: UARTS WITH FIFOS 14.4.2 Receive Buffer Register (RBR0, RBR1) This register is updated from the RX Shift Register at the end of a receive sequence. If the FIFOs are disabled, this register is undefined after reset. If the FIFOs are enabled, this register will return “0”...
  • Page 267 Chapter 14: UARTS WITH FIFOS 14.4.4.2 STB – Number of stop bits When set (“1”), two STOP bits are added after each character is sent, unless the character length is 5 when 1½ STOP bits are added. When cleared (“0”), one STOP bit is always added.

  • Page 268: Line Status Registers (Lsr0,Lsr1)

    Chapter 14: UARTS WITH FIFOS 14.4.5 Line Status Registers (LSR0,LSR1) Table 14-6 lists the fields of the Line Status Registers. Table 14-6 Line Status Register Fields Read Comment Data Ready Overrun Error Parity Error Framing Error Break Interrupt THRE TX Holding Register Empty TEMT Transmitter Empty FIFOERR...
  • Page 269 Chapter 14: UARTS WITH FIFOS 14.4.5.4 FE – Framing Error If the FIFOs are disabled, this bit is set if the received data did not have a valid STOP bit. This bit is reset when the G-Bus reads this register. If the FIFOs are enabled, the state of this bit is revealed to the G-Bus when the byte it refers to is at the top of the FIFO.

  • Page 270: Fifo Control Registers (Fcr0, Fcr1)

    Chapter 14: UARTS WITH FIFOS 14.4.6 FIFO Control Registers (FCR0, FCR1) Table 14-7 lists the fields of the FIFO Control Registers. These fields control the clearing and enabling of the FIFOs as well as the Receive FIFO Trigger level and DMA mode 1. Table 14-7 FIFO Control Register Field Descriptions Bit(s) Write...

  • Page 271: Interrupt Identification Registers (Iir0, Iir1)

    Chapter 14: UARTS WITH FIFOS RXRDY – Mode 1: Becomes active (Low) when the RX FIFO Trigger Level or Timeout occurs. Becomes inactive when the RX FIFO is empty. 14.4.6.5 RTFL0, 1 – Receive FIFO Trigger Level Table 14-8 lists the programmable trigger levels at which the amount of received data in the Receive FIFO will trigger an interrupt to service the FIFO.
  • Page 272 Chapter 14: UARTS WITH FIFOS Priority 4) Reading the Modem Status Register When multiple interrupts are pending, the interrupt line pulses Low after each service. After reset, D0 = “1”, D1 – D7 = “0”. 14.4.7.1 Receive Timeout Interrupt ID2 = “1” indicates an RX FIFO Character Timeout. A RX FIFO Character Timeout occurs if all of the following apply: 1.

  • Page 273: Interrupt Enable Registers (Ier0, Ier1)

    Chapter 14: UARTS WITH FIFOS 14.4.8 Interrupt Enable Registers (IER0, IER1) Table 14-11 details the functionality of the Interrupt Enable Register bit fields. Table 14-11 Fields of Interrupt Enable Registers Field Bit(s) Description Name – Reserved Enable Modem Status Interrupt. When set (“1”), an interrupt is generated if D0, D1, D2, or D3 of the EDSSI Modem Status Register have been set.

  • Page 274: Modem Status Registers (Msr0, Msr1)

    Chapter 14: UARTS WITH FIFOS 14.4.9.2 OUT2, OUT1, RTS and DTR These signals control the state of their corresponding outputs (OUT2*, OUT1*, RTS*, and DTR*) even in the Loop Mode. DTR* = “1” when DTR = “0”. (Same for OUT2, OUT1, & RTS) DTR* = “0”...

  • Page 275: Scratch Registers (Scr0, Scr1)

    Chapter 14: UARTS WITH FIFOS 14.4.10.5 DDCD – Delta Data Carry Detect This bit is set (“1”) if the state of DCD has changed since the Modem Status Register was last read. 14.4.10.6 TERI – Trailing Edge Ring Indicator This bit is set if the RI* input has changed from “0” to “1” since this register was last read. 14.4.10.7 DDSR –...

  • Page 276: Divisor Latch Ls And Ms Registers (Dll, Dlm)

    Chapter 14: UARTS WITH FIFOS 14.4.13 Divisor Latch LS and MS Registers (DLL, DLM) The table below shows the divisor needed to generate a prescaler output of approximately 8 MHz. The effective Clock Enable generated is 16x the required baud rate. Table 14-14 Prescaler output and divide values for various CPU &...

  • Page 277: S Pecial F Eatures

    Chapter 14: UARTS WITH FIFOS 14.5 Special Features This section discusses how and where the TX7901 UARTs differ from the original NS16550A device. 14.5.1 Transmit Machine Timing TXM (Transmit Machine) starts after 2 – 3 baud clock cycles from the time the TX Holding Register is written.

  • Page 278: I Mplemented Restrictions

    Chapter 14: UARTS WITH FIFOS 14.6 Implemented restrictions 14.6.1 Package pins For UART1, only SIN and SOUT arrive at the package pins. Other input signals are tied internally, and other output signals remain open. Outputs Inputs Level Remaining Open RCLK BAUD RCLK_BAUD OUT1...

  • Page 279: O Verview

    15.1 Overview Boot SPI consists of the TSEI serial port interface and Boot Memory sequencer for Word access (BM/W). TSEI is a Toshiba extended version of a serial peripheral interface (SPI) communication unit, which accesses serial ROM, serial RTC, etc.
  • Page 280 Chapter 15: Serial Port Interface SPI Memory Map (TSEI registers, GPIO registers, and Boot address area) 0x1FC1_0000 Boot address Area 0x1FC0_0000 0x1e00_A000 0x1e00_901C DDCR TSEI's 0x1e00_9018 SEDR data-direction, data, status,and 0x1e00_9014 SESR control registers 0x1e00_9010 SECR 0x1e00_900C Reserved General 0x1e00_9008 GPIO_outenab Purpose I/O 0x1e00_9004...

  • Page 281: B Oot M Emory S Equencer For W Ord A Ccess (Bm/W)

    Chapter 15: Serial Port Interface 15.2 Boot Memory Sequencer for Word Access (BM/W) When the Boot ROM address is on the G-Bus, BM/W detects the address and starts to access the SPI ROM on Port0. First, BM/W sets some parameters to TSEI. Table 15-2 TSEI Specifications Control Register (SECR) SEIE...
  • Page 282 Automatically shift the input data from MISO pin to Data Boot mode TASM Register when performing a read to the Data Register. Compatible mode: don’t care Normal Toshiba mode: 0 Disable automatic mode mode Enable automatic mode TMSE Boot mode...

  • Page 283: Boot Rom (64 Kb)

    Chapter 15: Serial Port Interface This is compatible with the Atmel AT25HP256/512. The bit rate is 2.08 MHz (fGBus = 66 MHz) or 1.56 MHz (fGBus = 50 MHz). = fGBus/4/SER. (See Figure 15-1 above.) BM/W locates the first byte on the LSB D[7:0], the second byte on D[15:8], third byte on D[23:16], and the fourth byte on D[31:24], regardless of the CPU endianness.
  • Page 284 Chapter 15: Serial Port Interface SPI External Interface & General Purpose I/O External SPI Devices SPI_CLK Serial EEPROM TSEI SPI_MISO Real Time Clock SPI_MOSI port0_out SPI_PORT0B SPI_PORT1B SPI_PORT2B SPI_PORT3B SPI_PORT4B SPI_PORT5B 0x1E00_9008 GPIO_outenab 0x1E00_9000 GPIO_outreg GPIO_inreg 0x1E00_9004 TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) 15-6...

  • Page 285: Tsei O Verview

    CS_n Figure 15-2 TSEI Block Diagram A special Toshiba operation mode allows the use of MicroDMAs with Toshiba’s line of 900/H CPUs, allowing automated data transfer of larger data-blocks without CPU utilization. TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

  • Page 286: Tsei T Ransfers

    Chapter 15: Serial Port Interface 15.4 TSEI Transfers During a TSEI transfer, data are simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronizes the shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave TSEI device;...

  • Page 287: Sdmiso And Sdmosi

    Cycle # SCK (CPOL=0) SCK (CPOL=1) MOSI MISO (Compatibility Mode) TSRC (Toshiba Mode) TSTC (Toshiba Mode) Master Slave Mode Mode Figure 15-3 CPHA Equals 0 Transfer Format In this transfer format, the first bit is shifted in on the first clock edge. This will be on a rising edge when CPOL equals 0 and on a falling edge when CPOL equals 1.

  • Page 288: Cpha Equals 1 Format

    In both the Master Mode and the Slave Mode, the SEF flag (in the Compatibility Mode) or the TSRC and TSTC flags (in the Toshiba Mode) will be asserted simultaneously after the last shift cycle completes. Any attempt to write to this register while the data shifting is still in progress will result in a write collision.

  • Page 289: Mcu I Nterface

    Chapter 15: Serial Port Interface 15.7 MCU Interface Figure 15-5 shows the transactions for the TSEI MCU Interface. In particular, it shows a read access followed by a write access. SimWave 3.15-E Mon Dec 7 14:06:42 1998 TB_TSEI.CPU_CLK TB_TSEI.CS_n TB_TSEI.RD_n TB_TSEI.WR_n TB_TSEI.WAIT_n TB_TSEI.AD...

  • Page 290: Tsei Registers

    0: TSEI interrupts are disabled. Polling is used to sense the SEIF and MODF flags. 1: A TSEI interrupt is requested if SEF or MODF is being asserted. Toshiba Mode: This flag is obsolete in the Toshiba mode. Only the Interrupt Controller registers are used to enable or disable interrupts. SEE: TSEI System Enable 0: TSEI system is off.

  • Page 291: Tsei Status Register (Sesr)

    TSEI system and is used to switch between the TSEI operation modes. The status flags can be cleared only in the Toshiba Mode by writing a “1” to them. Writing a “0” value to these flags has no effect.
  • Page 292 It is cleared by reading SESR with the SOVF bit set, then accessing SEDR. Switching to the Master Mode will also clear the flag. Toshiba Mode: The TSRC flag is used instead of the TSEF flag to determine whether the Data Register has been read out.
  • Page 293 Selects a special Toshiba mode that also allows MicroDMA transfers to be performed with Toshiba’s line of 900/H CPUs. It is necessary to disable the TSEI system before switching to the Toshiba operating mode. After switching to the Compatibility Mode, the TSRC and the TSTC flags are ignored.

  • Page 294: Tsei Data Register (Sedr)

    Chapter 15: Serial Port Interface 15.8.3 TSEI Data Register (SEDR) This register is the data register of the TSEI system. data7 data6 data5 data4 data3 data2 data1 data0 Reset: When the TSEI system is configured as a master, transfers are started by a software write to the SEDR register.

  • Page 295: Tsei S Ystem E Rrors

    Chapter 15: Serial Port Interface When the TSEI system is enabled as a master, bit 3 in the DDCR register must be set to “1” to enable the master serial data output. If a master device needs to initiate a TSEI transfer to receive a byte of data from a slave without transmitting a byte, it might purposely leave the TSDMOSI output disabled.

  • Page 296: Toshiba Mode

    Interrupt on TSRC TSEI Interrupt Channel 2 (TSIC2) Interrupt on TSTC The SEIE bit is obsolete in the Toshiba Mode. The Interrupts are individually disabled at the interrupt controller. 15.10.3 Interrupt Generation on TSIC0 If a flag in the SESR register that causes an interrupt shows a transition from “0” to “1,” an interrupt will be generated if no other interrupt flag is already pending.

  • Page 297: Mode

    Chapter 15: Serial Port Interface Example: SEF Flag MODF Flag Clear SEF TSCI0 Figure 15-6 TSIC0 behavior, Compatibility Mode In the example above, the SEF flag is asserted after a completed transfer. On the transition of this flag from “0” to “1,” an IRQ signal is caused on TSIC0. This will be a pulse that is one clock cycle in length.

  • Page 298: Chapter 16. Clocks

    Chapter 16: Clocks 16. Clocks 16.1 Overview Clocks are one of the fundamental elements of the TX7901, which has three main clock domains, which are depicted in Figure 16-1 and summarized in Table 16-1. By manipulating the internal clock in different ways, the TX7901 can be controlled to run in different modes, and at different clock speeds.

  • Page 299: F Eatures

    Chapter 16: Clocks 16.2 Features The main features of the TX7901 clocks are as follows: • f/2, f/3, f/4 dividers are available for the CPU:SysBus clocks • Fixed f/2 divider for sysBus:gbusClock • PLL and divider bypass for scan and memory test modes TX7901 User’s Manual (Rev.
  • Page 300 Chapter 16: Clocks TX7901 CLOCK DOMAINS CPU Clock System Bus Clock G-bus Clock I$32K D$32K DEBUG SDRAM MEMORY Controller C790 64-Bit DMAC G-Bus Bridge PCIC Timer Counter UART TIMIN BAUDO (0+ ~ 33/25 MHz) TXCLK PCI CLK (50 Hz ~ (2.5 /10/ 25 (0+~66 MHz) 256 KHz)

  • Page 301: D Iagram

    Chapter 16: Clocks PLL SyncExt SDRAM DIMMS PLL SyncOut PLL SyncIn PLL Feedback CpuClk RefClk SysClk PllSel[1:0] DivSel[1:0] GbusClk DivSel== div1 IP Block divRst IPclk IFclk extIPclk sysReset Figure 16-2 TX7901 Clock Distribution Diagram TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) 16-4...

  • Page 302: O Peration

    Chapter 16: Clocks 16.3 Operation The TX7901 relies on one external reference clock source (refClk) and on-chip phased- locked loop for generating various clocks, as shown in the above Figure. pllSel[1:0]) signals are used to select either PLL or bypass PLL. Table 16-2 PLL Selection PllSel[1:0] Clock Source...

  • Page 303: P Eripheral M Odule C Lock

    Chapter 16: Clocks Table 16-4 Example Frequency Relationship CpuClk RefClk SysClk gbusClk 133 MHz 266* 400* 533* 133 MHz 66 MHz 100 MHz 300* 400* 100 MHz 50 MHz 66 MHz 66 MHz 33 MHz 50 MHz 50 MHz 25 MHz * 1: Premium products only.

  • Page 304: Spi Clock

    Chapter 16: Clocks 16.4.3 SPI Clock The SPI module operates in the Master Mode. When in the Master Mode, SPI needs to drive the clock to the external slaves. The SPI and G-Bus interface both synchronize Read and Write Control signals between the G-Bus Clock and the SPI clock in order to perform data register access.

  • Page 305: Chapter 17. Pins

    Chapter 17: Pins 17. Pins This chapter details the physical pins of the TX7901. Table 17-1 describes the functionality of each group of pins, while Table 17-2 specifies the allocation of pin positions for each individual signal. Table 17-1 TX7901 Pin Functionality Rev.2.0 pinout Name of Signal Function...
  • Page 306 Chapter 17: Pins Name of Signal Function SdmBAddr[1:0] SDRAM Bank Address bits SdmCSB[3:0] SDRAM Chip select for each DIMM sdmCASB SDRAM CAS signal sdmRASB SDRAM RAS signal sdmWrB SDRAM Write Enable sdmCKE SDRAM Clock enable UART0 Interface Receive/Transmit clock derived from CLK divided by the value in the divisor latch UA0_BAUD DLL &...
  • Page 307 Chapter 17: Pins Name of Signal Function MAC1_MDC MII Management Clock MAC1_MDIO MII Management Data Input/Output MAC1_HwFDupSel Full Duplex Select Timer/Counter Interface TIMOUT1 Timer 1 Output TIMIN1 External Clock Input for Timer 1 TIMOUT2 Timer 2 Output TIMIN2 External Clock Input for Timer 2 Serial Peripheral Interface SPI_MISO Serial Data Input...
  • Page 308 Chapter 17: Pins Name of Signal Function PCI1_TRDYB Target Ready PCI1_IRDYB Initiator Ready PCI_STOPB Indicates that the current Target is requesting Initiator to stop the PCI1_STOPB current transaction. Device select; it indicates that the current driving device has decoded its address PCI1_DEVSELB as the target of the current access.

  • Page 309: Jtag B Oundary S Can External Test Chain Configuration

    Chapter 17: Pins 17.1 JTAG Boundary Scan external test chain configuration Please contact Toshiba to request a BSDL file based on IEEE1149.1b. This file contains the required information. TX7901 User’s Manual (Rev. 6.30T – Nov, 2001) 17-5...

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