Toshiba TLCS-900/L1 Series Manual page 87

7
B0CS
Bit symbol B0E
(00C0H)
Read/Write W
After reset 0
Read-
Function 0: Disable
modify-
1: Enable
write
instructions
are
prohibited.
B1CS
Bit symbol B1E
(00C1H)
Read/Write W
After reset 0
Read-
Function 0: Disable
modify-
1: Enable
write
instructions
are
prohibited.
B2CS
Bit symbol B2E
(00C2H)
Read/Write
After reset 1
Read-
Functions 0: Disable
modify-
1: Enable
write
instructions
are
prohibited.
B3CS
Bit symbol B3E
(00C3H)
Read/Write W
After reset 0
Read-
Functions 0: Disable
modify-
1: Enable
write
instructions
are
prohibited.
BEXCS
Bit symbol
(00C7H)
Read/Write
After reset
Read-
Functions
modify-
write
instructions
are
prohibited.
Master enable bit
0 Enable
1 Disable
CS2 area selection
0 16-Mbyte area
1 Specified address area
6 5 4
B0OM1 B0OM0
0 0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10: Don't care
11:
B1OM1 B1OM0
0 0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10: Don't care
11:
B2M B2OM1 B2OM0
0 0 0
CS2 area Chip select output
selection waveform selection
0: 16-Mbyte 00: For ROM/SRAM
area 01:
1: CS area 10: Don't care
11:
B3OM1 B3OM0
0 0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10: Don't care
11:
Chip select output
waveform selection
00 For ROM/SRAM
01
10 Don't care
11
Figure 3.6.5 Chip Select/Wait Control Registers
91C824-85
3 2 1
B0BUS B0W2 B0W1
W
0 0 0
Data bus Number of waits
width 000: 2 waits
0: 16 bits 001: 1 wait
010: (1 + N) waits 110: 4 waits
1: 8 bits
011: 0 waits
B1BUS B1W2 B1W1
W
0 0 0
Data bus Number of waits
width 000: 2 waits
0: 16 bits 001: 1 wait
010: (1 + N) waits 110: 4 waits
1: 8 bits
011: 0 waits
B2BUS B2W2 B2W1
W
0 0 0
Data bus Number of waits
width 000: 2 waits
0: 16 bits 001: 1 wait
010: (1 + N) waits 110: 4 waits
1: 8 bits
011: 0 waits
B3BUS B3W2 B3W1
W
0 0 0
Data bus Number of waits
width 000: 2 waits
0: 16 bits 001: 1 wait
010: (1 + N) waits 110: 4 waits
1: 8 bits
011: 0 waits
BEXBUS BEXW2 BEXW1
W
0 0 0
Data bus Number of waits
width 000: 2 waits
0: 16 bits 001: 1 wait
010: (1 + N) waits 110: 4 waits
1: 8 bits
011: 0 waits
Number of address area waits
(See 3.6.2, (3) Wait control.)
Data bus width selection
0 16-bit data bus
1 8-bit data bus
TMP91C824
0
B0W0
0
100: Reserved
101: 3 waits
111: 8 waits
B1W0
0
100: Reserved
101: 3 waits
111: 8 waits
B2W0
0
100: Reserved
101: 3 waits
111: 8 waits
B3W0
0
100: Reserved
101: 3 waits
111: 8 waits
BEXW0
0
100: Reserved
101: 3 waits
111: 8 waits
2008-02-20