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c.
STOP mode
When STOP mode is selected, all internal circuits stop, including the internal
oscillator pin status in STOP mode depends on the settings in the SYSCR2<DRVE>
register. Table 3.3.6, Table 3.3.7 summarizes the state of these pins in STOP mode.
After STOP mode has been cleared system clock output starts when the warm-up
time has elapsed, in order to allow oscillation to stabilize. After STOP mode has been
cleared, either NORMAL mode or SLOW mode can be selected using the
SYSCR0<RSYSCK> register. Therefore, <RSYSCK>, <RXEN> and <RXTEN> must
be set See the sample warm-up times in Table 3.3.5.
Figure 3.3.8 illustrates the timing for clearance of the STOP mode halt state by an
interrupt.
X1
A0 to A23
D0 to D15
RD
WR
Interrupt for
release
Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt
Table 3.3.5 Sample Warm-up Times after Clearance of STOP Mode
SYSCR0
<RSYSCK>
0 (fc)
1 (fs)
Warm-up
time
Data
STOP
mode
SYSCR2<WUPTM1:0>
8
01 (2
)
10 (2
8 µs
0.496 ms
7.8 ms
500 ms
91C824-33
= 33 MHz, fs = 32.768 kHz
at f
OSCH
14
16
)
11 (2
)
1.986 ms
2000 ms
TMP91C824
Data
2008-02-20
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