Toshiba TLCS-900/L1 Series Manual page 146

b. Receiving
and the data is shifted to receiving buffer 1. This starts when the receive
interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-
bit data are received, the data will be transferred to receiving buffer 2 (SC0BUF
according to the timing shown below) and INTES0<IRX0C> will be set to
generate INTRX0 interrupt.
IRX0C
(INTRX0
interrupt request)
SCLK0 output
(<SCLKS>=0
Rising edge mode)
SCLK0 output
(<SCLKS>=1
Fallingf edge mode)
RXD0
Figure 3.9.21 Receiving Operation in I/O Interface Mode (SCLK0 output mode)
input becomes active after the receive interrupt flag INTES0<IRX0C> is cleared
by reading the received data. When 8-bit data is received, the data will be shifted
to receiving buffer 2 (SC0BUF according to the timing shown below) and
INTES0<IRX0C> will be set again to be generate INTRX0 interrupt.
SCLK0input
(<SCLKS> = 0:
Rising edge mode)
SCLK0 input
(<SCLKS> = 1:
Falling edge mode)
RXD0
IRX0C
(INTRX0 )
Figure 3.9.22 Receiving Operation in I/O Interface Mode (SCLK0 input mode)
Note: The system must be put in the receive enable state (SCMOD0<RXE> = 1)
In SCLK output mode, the synchronous clock is outputted from SCLK0 pin
The outputting for the first SCLK0 starts by setting SC0MOD0<RXE> to 1.
Bit0
In SCLK input mode, the data is shifted to receiving buffer 1 when the SCLK
Bit0 Bit1
before data can be received.
91C824-144
Bit1 Bit6
Bit5 Bit6
TMP91C824
Bit7
Bit7
2008-02-20