Toshiba TLCS-900/L1 Series Manual page 195

The watchdog timer consists of a 22-stage binary counter which uses the system clock
(f ) as the input clock. The binary counter can output f
SYS
f /2 .
21
SYS
WDT counter
n
WDT interrupt
WDT clear
(Software)
The runaway is detected when an overflow occurs, and the watchdog timer can reset
device. In this case, the reset time will be between 22 and 29 states (21.3~28.1 µs at f
= 33MHz, f = 2.2 MHz) is f
FPH
oscillator clock (f
OSCH
n
WDT counter
WDT interrupt
Internal reset
Overflow
Figure 3.12.2 NORMAL Mode
/2, where f
FPH FPH
) by sixteen through the clock gear function.
Overflow
22 to 29 states
(21.3 to 28.1µs at f
OSCH
Figure 3.12.3 Reset Mode
91C824-193
/2 , f /2
15
SYS SYS
Write clear code
is generated by diving the high-speed
= 33 MHz, f = 2.2 MHz)
FPH
TMP91C824
, f /2 and
17 19
SYS
0
OSCH
2008-02-20