External Interrupt Control - Toshiba TLCS-900/L1 Series Manual

(2) External interrupt control

Name Address
Symbol
Interrupt 8CH
Always
input
IIMC
write 0
mode (Prohibit
control RMW)
INT0 level enable
0 edge detect INT
1 H level INT
rising edge enable
NMI
0 INT request generation at falling edge
1 INT request generation at rising/falling edge
(3) Interrupt request flag clear register
The interrupt request flag is cleared by writing the appropriate micro DMA start
vector, as given in Table 3.4.1, to the register INTCLR.
For example, to clear the interrupt flag INT0, perform the following register
operation after execution of the DI instruction.
INTCLR ← 0AH: Clears interrupt request flag INT0.
Name Address
Symbol
Interrupt 88H
INTCLR clear (Prohibit
control RMW)
(4) Micro DMA start vector registers
This register assigns micro DMA processing to which interrupt source. The
interrupt source with a micro DMA start vector that matches the vector set in this
register is assigned as the micro DMA start source.
When the micro DMA transfer counter value reaches zero, the micro DMA transfer
end interrupt corresponding to the channel is sent to the interrupt controller, the
micro DMA start vector register is cleared, and the micro DMA start source for the
channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA
start vector register again during the processing of the micro DMA transfer end
interrupt.
If the same vector is set in the micro DMA start vector registers of more than one
channel, the channel with the lowest number has a higher priority.
Accordingly, if the same vector is set in the micro DMA start vector registers of two
channels, the interrupt generated in the channel with the lower number is executed
until micro DMA transfer is complete. If the micro DMA start vector for this channel
is not set again, the next micro DMA is started for the channel with the higher
number (Micro DMA chaining).
7 6 5
− −
I3EDGE
0 0 0
Always INT3EDGE
write 0 0: Rising
1: Falling
7 6 5
CLRV5
0
91C824-49
4 3 2
I2EDGE I1EDGE I0EDGE
W
0 0 0
INT2EDGE INT1EDGE INT0EDGE
0: Rising 0: Rising 0: Rising
1: Falling 1: Falling 1: Falling
4 3 2
CLRV4 CLRV3 CLRV2
W
0 0 0
Interrupt vector
TMP91C824
1 0
I0LE NMIREE
0 0
INT0 mode 1: Operates
0: Edge even on
1: Level rising/
falling
edge of
NMI
1 0
CLRV1 CLRV0
0 0
2008-02-20