Toshiba TLCS-900/L1 Series Manual page 243

(3) Interrupt control (3/3)
Symbol Name Address
DMA 0
DMA0V request 80H
vector
DMA 1
DMA1V request 81H
vector
DMA 2
DMA2V request 82H
vector
DMA 3
DMA3V request 83H
vector
Interrupt 88H
INTCLR clear (Prohibit
control RMW)
DMA
89H
software
DMAR (Prohibit
request
RMW)
register
DMA
burst
DMAB 8AH
request
register
Interrupt 8CH
input
IIMC
mode (Prohibit
control RMW)
7 6 5
DMA0V5
0
DMA1V5
0
DMA2V5
0
DMA3V5
0
CLRV5
0
Clears interrupt request flag by writing to DMA start vector
− −
I3EDGE
W W W
0 0 0
Always Always INT3 edge
write 0 write 0 0: Rising
1: Falling
91C824-241
4 3 2
DMA0V4 DMA0V3 DMA0V2
R/W
0 0 0
DMA0 start vector
DMA1V4 DMA1V3 DMA1V2
R/W
0 0 0
DMA1 start vector
DMA2V4 DMA2V3 DMA2V2
R/W
0 0 0
DMA2 start vector
DMA3V4 DMA3V3 DMA3V2
R/W
0 0 0
DMA3 start vector
CLRV4 CLRV3 CLRV2
W
0 0 0
DMAR3 DMAR2
R/W R/W
0 0
1: DMA request in software
DMAB3 DMAB2
R/W R/W
0 0
1 : DMA request on burst mode
I2EDGE I1EDGE I0EDGE
W W W
0 0 0
INT2 edge INT1 edge INT0 edge
0: Rising 0: Rising 0: Rising
1: Falling 1: Falling 1: Falling
TMP91C824
1 0
DMA0V1 DMA0V0
0 0
DMA1V1 DMA1V0
0 0
DMA2V1 DMA2V0
0 0
DMA3V1 DMA3V0
0 0
CLRV1 CLRV0
0 0
DMAR1 DMAR0
R/W R/W
0 0
DMAB1 DMAB0
R/W R/W
0 0
I0LE NMIREE
W W
0 0
INT0 1: O
peration
0: Edge
even on
1: Level
NMI
rising
edge
2008-02-20