Toshiba TLCS-900/L1 Series Manual page 164

(6) Transmitter/receiver selection
Set the SBI0CR2<TRX> to 1 for operating the TMP91C824 as a transmitter. Clear
the <TRX> to 0 for operation as a receiver. When data with an addressing format is
transferred in slave mode, when a slave address with the same value that an I2C0AR
or a GENERAL CALL is received (All 8-bit data are 0 after a start condition), the
<TRX> is set to 1 by the hardware if the direction bit (
device is 1, and is cleared to 0 by the hardware if the bit is 0. In the master mode,
after an acknowledge signal is returned from the slave device, the <TRX> is cleared to
0 by the hardware if a transmitted direction bit is 1, and is set to 1 by the hardware if
it is 0. When an acknowledge signal is not returned, the current condition is
maintained.
The <TRX> is cleared to 0 by the hardware after a stop condition on the I
detected or arbitration is lost.
(7) Start/stop condition generation
When the SBI0SR<BB> is 0, slave address and direction bit which are set to
SBI0DBR are output on a bus after generating a start condition by writing 1 to the
SBI0CR2<MST, TRX, BB, PIN>. It is necessary to set transmitted data to the data
buffer register SBI0DBR and set 1 to <ACK> beforehand.
SCL line 1
SDA line A6
Start condition
Figure 3.10.9 Start Condition Generation and Slave Address Generation
When the <BB> is 1, a sequence of generating a stop condition is started by writing
1 to the <MST, TRX, PIN>, and 0 to the <BB>. Do not modify the contents of <MST,
TRX, BB, PIN> until a stop condition is generated on a bus.
SCL line
SDA line
Figure 3.10.10 Stop Condition Generation
The state of the bus can be ascertained by reading the contents of SBI0SR<BB>.
SBI0SR<BB> will be set to 1 if a start condition has been detected on the bus, and
will be cleared to 0 if a stop condition has been detected.
And about generation of stop condition in master mode, there are some limitation
points. Please refer to the 3.10.6 (4) "Stop condition generation".
2 3 4 5
A5 A4 A3 A2
Slave address and the direction bit
Stop condition
91C824-162
TMP91C824
) sent from the master
R / W
6 7 8 9
A1 A0
R / W
Acknowledge
signal
2008-02-20
C bus is
2