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(8) UART/serial channel (2/2)
(8-3) UART/SIO channel1
Symbol
Name
Address
Serial
208H
SC1BUF
channel 1
(Prohibit
buffer
RMW)
Serial
SC1CR
channel 1
209H
control
Serial
SC1MOD0
channel 1
20AH
mode
Baud rate
BR1CR
20BH
control
Serial
channel 1
BR1ADD
20CH
K setting
register
Serial
SC1MOD1
channel 1
20DH
mode1
7
6
5
RB7/TB7
RB6/TB6
RB5/TB5
R (Receiving)/W (Transmission)
RB8
EVEN
PE
R
R/W
Undefined
0
0
Receiving
Parity
1: Parity
data bit8
0: Odd
Enable
1: Even
TB8
CTSE
RXE
0
0
0
CTS
Receive
1:
1:
Transmission
enable
enable
data bit8
−
BR1ADDE
BR1CK1
0
0
0
00: φT0
1: (16 − K)/16
Always
01: φT2
write 0
divided
10: φT8
enable
11: φT32
I2S1
FDPX1
R/W
R/W
0
0
IDLE2
Duplex
0: Stop
0: Half
1: Operate
1: Full
91C824-249
4
3
2
RB4/TB4
RB3/TB3
RB2/TB2
Undefined
OERR
PERR
FERR
R (Cleared to 0 by reading)
0
0
0
1: Error
Overrun
Parity
Framing
WU
SM1
SM0
R/W
0
0
0
1: Wakeup
00: I/O interface
01: UART 7 bits
10: UART 8 bits
11: UART 9 bits
BR1CK
BR1S3
BR1S2
R/W
0
0
0
Setting the divided frequency "N"
(0 to F)
BR1K3
BR1K2
0
0
Sets the frequency divisor "K"
(Divided by N + (16 − K)/16)
TMP91C824
1
0
RB1/TB1
RB0/TB0
SCLKS
IOC
R/W
0
0
0: SCLK1↑
1: Input
1: SCLK1↓
SC1
SC0
0
0
00: TA0TRG
01: Baud rate generator
10: Internal clock f
SYS
11: External clock SCLK1
BR1S1
BR1S0
0
0
BR1K1
BR1K0
R/W
0
0
2008-02-20
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