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Prescaler
φT0
2
8
4
φT2
Serial clock generation circuit
BR1CR
<BR1CK1:0>
<BR1S3:0>
φT0
φT2
φT8
φT32
f
SYS
SCLK1
Concurrent
with PC5
I/O interface mode
SCLK1
Concurrent
with PC5
Receive
counter
(UART only ÷ 16)
RXDCLK
SC1MOD0
Receive control
<RXE>
Receive buffer 1 (Shift register)
RXD1
Concurrent
with PC4
RB8
Receive buffer 2 (SC1BUF)
Figure 3.9.3 Block Diagram of the Serial Channel 1 (SIO1)
16 32 64
φT8 φT32
TA0TRG
(from TMRA0)
BR1CR
BR1ADD
<BR1K3:0>
BR1CR
<BR1ADDE>
SC1MOD0
Baud rate
<SC1:0>
generator
÷2
SC1CR
Serial channel
SC1MOD0
interrupt
<WU>
control
SC1CR
<PE>
<EVEN>
Parity control
Error flag
SC1CR
<OERR><PERR><FERR>
Internal data bus
91C824-124
UART
SIOCLK
mode
SC1MOD0
<SM1:0>
I/O
interface mode
<IOC>
Transmision
counter
(UART only ÷ 16)
TXDCLK
Transmission
control
TB8
Transmission buffer (SC1BUF)
TMP91C824
INT request
INTRX1
INTTX1
CTS1
Concurrent
with PC5
SC1MOD0
<CTSE>
TXD1
Concurrent
with PC3
2008-02-20
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