Toshiba TLCS-900/L1 Series Manual page 86

(4) Address area size specification
Table 3.6.1 shows the relationship between CS area and area size. "∆" indicates
areas that cannot be set by memory start address register and address mask register
combinations. When setting an area size using a combination indicated by "∆", set the
start address mask register in the desired steps starting from 000000H.
If the CS2 area is set to 16-Mbytes or if two or more areas overlap, the smaller CS
area number has the higher priority.
Example: To set the area size for CS0 to 128 Kbytes:
a. Valid start addresses
000000H
020000H
040000H
060000H
b. Invalid start addresses
000000H
010000H
030000H
050000H
Size (Bytes)
256 512
CS Area
○ ○
CS0
○ ○
CS1
CS2
CS3
Note: "∆" indicates areas that cannot be set by memory start address register and address mask
register combinations.
3.6.2 Chip Select/Wait Control Registers
Figure 3.6.5 lists the chip select/wait control registers.
The master enable/disable, chip select output waveform, data bus width and number of
wait states for each address area (CS0 to CS3 and others) are set in their respective chip
select/wait control registers, B0CS to B3CS and BEXCS.
128 Kbytes
128 Kbytes
Any of these addresses may be set as the start address.
128 Kbytes
This is not an integer multiple of the desired area size
64 Kbytes
setting. Hence, none of these addresses can be set as
128 Kbytes
the start address.
128 Kbytes
Table 3.6.1 Valid Area Sizes for Each CS Area
32 K 64 K 128 K 256 K 512 K
○ ○
∆
○
∆
○ ○
∆
○ ○
∆
91C824-84
1 M 2 M
∆ ∆ ∆ ∆
∆ ∆ ∆ ∆
∆ ∆ ∆ ∆
∆ ∆ ∆ ∆
TMP91C824
4 M 8 M
∆
∆ ∆
∆ ∆
2008-02-20