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software polling 6-6
,
hardware reset 6-22
6-31
HI08-to-DSP core interface 6-1
HI08-to-host
interface 6-2
Host Base Address Register (HBAR) 6-13
6-33
programming sheet B-22
,
host command 6-8
6-23
Host Control Register (HCR) 6-13
Host Command Interrupt Enable (HCIE) 6-14
Host Flags 2, 3 (HF) 6-14
Host Receive Interrupt Enable (HRIE) 6-15
Host Transmit Interrupt Enable (HTIE) 6-14
programming sheet B-23
Host Data Direction Register (HDDR) 6-4
6-16
programming sheet B-34
Host Data Direction Register (HDRR) 6-33
Host Data Register (HDR) 6-13
programming sheet B-34
host interrupt request pins (IRQx) 6-9
Host Port Control Register (HPCR) 6-4
,
,
6-22
6-32
6-33
Host Acknowledge Enable (HAEN) 6-20
Host Acknowledge Polarity (HAP) 6-18
Host Address Line 8 Enable (HA8EN) 6-20
Host Address Line 9 Enable (HA9EN) 6-20
7-20
Host Address Strobe Polarity (HASP) 6-19
Host Chip Select Enable (HCSEN) 6-20
Host Chip Select Polarity (HCSP) 6-18
Host Data Strobe Polarity (HDSP) 6-19
Host Dual Data Strobe (HDDS) 6-19
Host Enable (HEN) 6-19
Host GPIO Port Enable (HGEN) 6-20
Host Multiplexed Bus (HMUX) 6-19
Host Request Enable (HREN) 6-20
Host Request Open Drain (HROD) 6-19
Host Request Polarity (HRP) 6-18
programming sheet B-5
host processor registers 6-13
Host Receive (HRX) register 6-6
Host Receive Data Register (HRX) 6-22
Host Receive Request (HRRQ) 6-9
host request line 6-4
host request pins 6-10
host side
Command Vector Register (CVR) 6-26
Interface Control Register (ICR) 6-24
Interface Status Register (ISR) 6-27
Interface Vector Register (IVR) 6-29
Receive Byte Registers (RXH, RXM, RXL) 6-30
Index-6
,
,
6-17
,
6-32
,
,
6-13
,
,
6-16
6-33
,
,
,
6-13
6-18
,
,
B-22
,
,
6-22
6-33
DSP56303 User's Manual
Transmit Byte Registers (TXH, TXM,
TXL) 6-30
host side registers after reset 6-31
Host Status Register (HSR) 6-13
Host Command Pending (HCP) 6-15
Host Flags 0, 1 (HF) 6-15
Host Receive Data Full (HRDF) 6-16
Host Transmit Data Empty (HTDE) 6-15
Host Transmit (HTX) register 6-7
Host Transmit Data Register (HTDR)
programming sheet B-21
host-side
register map 6-24
host-to-DSP
,
data transfers 6-6
6-22
data word 6-1
handshaking protocols 6-1
instructions 6-1
mapping 6-1
HREQ/HTRQ handshake flags 6-23
instructions and addressing modes. 6-4
Interface Control Register (ICR) 6-23
Double Host Request (HDRQ) 6-9
Host Flag 0 (HF0) 6-25
Host Flag 1 (HF1) 6-25
Host Little Endian (HLEND) 6-25
Initialize (INIT) 6-25
Receive Request Enable (RREQ) 6-26
Transmit Request Enable (TREQ) 6-26
Interface Status Register (ISR) 6-23
Host Flag 2 (HF2) 6-28
Host Flag 3 (HF3) 6-28
Host Request (HREQ) 6-28
Receive Data Full (RDF) 6-7
Receive Data Register Full (RXDF) 6-29
Transmit Data Empty (TDE) 6-7
Transmit Data Register Empty (TXDE) 6-29
Transmitter Ready (TRDY) 6-28
interrupt routines 6-8
Interrupt Vector Register (IVR) 6-23
programming sheet B-25
interrupt-based techniques 6-23
masking interrupts 6-8
MOVEP instruction 6-13
,
multiplexed bus mode 6-4
non-multiplexed bus mode 6-4
pipeline 6-6
,
polling techniques 6-23
6-29
programming model
DSP side 6-13
host side 6-23
quick reference 6-32
Receive Byte Registers (RXH, RHM, RHL) 6-7
,
,
6-15
6-33
,
,
,
6-21
6-30
6-33
,
B-25
,
6-24
,
6-25
,
6-27
,
6-29
,
6-17
6-20
,
6-20
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