Watchdog Toggle (Mode 10) - Motorola DSP56303 User Manual

Operating Modes

9.3.4.2 Watchdog Toggle (Mode 10)

Bit Settings
TC3 TC2 TC1
1 0 1
In Mode 10, the timer toggles an external signal after a preset period. The
the value of the INV bit.When the counter equals the value in the TCPR, TCSR[TCF] is set,
and a compare interrupt is generated if the TCSR[TCIE] bit is also set. If the TCSR[TRM] bit
is set, the counter loads with the TLR value on the next timer clock and the count resumes.
Therefore, TRM = 1 is not useful for watchdog functions. If the TCSR[TRM] bit is cleared,
the counter continues to increment on each subsequent timer clock. When a counter overflow
occurs, the polarity of the
TLR is written with a new value while the TCSR[TE] bit is set. This process repeats until the
timer is disabled. In Mode 10, internal logic preserves the
additional 2.5 internal clock cycles after the hardware
convention ensures that a valid reset signal is generated when the
DSP56303.
Mode 10 (internal clock): TRM = 0
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter (TCR)
TCPR
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TOIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
9-24
TC0 Mode
0 10 Toggle
output signal is inverted. The counter is reloaded whenever the
TIO
first event
N
0
N
M
float
low
float
high
Figure 9-19. Watchdog Toggle Mode
DSP56303 User's Manual
Mode Characteristics
Name Function
Watchdog
value and direction for an
TIO
signal is asserted. This
RESET
TRM = 1 is not useful for watchdog function
M
N + 1
TIO Clock
Output Internal
signal is set to
TIO
signal resets the
TIO
M + 1 0
1