Internal I/O Memory Map
Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)
Peripheral
16-Bit Address
DMA3
DMA4
DMA5
Port B
B-4
24-Bit Address
$FFE3
$FFFFE3
$FFE2
$FFFFE2
$FFE1
$FFFFE1
$FFE0
$FFFFE0
$FFDF
$FFFFDF
$FFDE
$FFFFDE
$FFDD
$FFFFDD
$FFDC
$FFFFDC
$FFDB
$FFFFDB
$FFDA
$FFFFDA
$FFD9
$FFFFD9
$FFD8
$FFFFD8
$FFD7
$FFFFD7
$FFD6
$FFFFD6
$FFD5
$FFFFD5
$FFD4
$FFFFD4
$FFD3
$FFFFD3
$FFD2
$FFFFD2
$FFD1
$FFFFD1
$FFD0
$FFFFD0
$FFCF
$FFFFCF
$FFCE
$FFFFCE
$FFCD
$FFFFCD
$FFCC
$FFFFCC
$FFCB
$FFFFCB
$FFCA
$FFFFCA
$FFC9
$FFFFC9
$FFC8
$FFFFC8
DSP56303 User's Manual
Register Name
DMA Source Address Register (DSR3)
DMA Destination Address Register (DDR3)
DMA Counter (DCO3)
DMA Control Register (DCR3)
DMA Source Address Register (DSR4)
DMA Destination Address Register (DDR4)
DMA Counter (DCO4)
DMA Control Register (DCR4)
DMA Source Address Register (DSR5)
DMA Destination Address Register (DDR5)
DMA Counter (DCO5)
DMA Control Register (DCR5)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Host Port GPIO Data Register (HDR)
Host Port GPIO Direction Register (HDDR)