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1.5.2
Address Generation Unit (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to
address data operands in memory and contains the registers that generate the addresses. It
implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and
reverse-carry. The AGU operates in parallel with other chip resources to minimize
address-generation overhead.
The AGU is divided into halves, each with its own identical address ALU. Each address ALU
has four sets of register triplets, and each register triplet includes an address register, offset
register, and modifier register. Each contains a 24-bit full adder (called an offset adder). A
second full adder (called a modulo adder) adds the summed result of the first full adder to a
modulo value that is stored in its respective modifier register. A third full adder (called a
reverse-carry adder) is also provided. The offset adder and the reverse-carry adder work in
parallel and share common inputs. The only difference between them is that the carry
propagates in opposite directions. Test logic determines which of the three summed results of
the full adders is output.
Each address ALU can update one address register from its own address register file during
one instruction cycle. The contents of the associated modifier register specify the type of
arithmetic used in the address register update calculation. The modifier value is decoded in
the address ALU.
1.5.3
Program Control Unit (PCU)
The PCU fetches and decodes instructions, controls hardware DO loops, and processes
exceptions. Its seven-stage pipeline controls the different processing states of the DSP56300
core. The PCU consists of three hardware blocks:
Program decode controller — decodes the 24-bit instruction loaded into the instruction
latch and generates all signals for pipeline control.
Program address generator — contains all the hardware needed for program address
generation, system stack, and loop control.
Program interrupt controller — arbitrates among all interrupt requests (internal
interrupts, as well as the five external requests
generates the appropriate interrupt vector address.
PCU features include the following:
Position-independent code support
Addressing modes optimized for DSP applications (including immediate offsets)
On-chip instruction cache controller
,
IRQA
IRQB
Overview
DSP56300 Core Functional Blocks
,
,
, and
IRQC
IRQD
NMI
), and
1-7
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