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initialization 7-6
initialization example 7-7
internally generated clock and frame sync 7-7
interrupt 7-7
Interrupt Service Routine (ISR) 7-9
interrupt trigger event 7-9
interrupts 7-7
multiple serial device selection 7-4
network enhancements 7-2
,
Network mode 7-2
7-8
,
Normal mode 7-2
7-10
On-Demand mode 7-10
,
operating mode 7-6
7-10
polling 7-7
Port Control Register (PCR) 7-6
Port Control Register C (PCRC) 7-36
Port Control Register D (PCRD) 7-36
Port Data Register (PDR) 7-38
Port Data Register C (PDRC) 7-38
Port Data Register D (PDRD) 7-38
Port Direction Register (PRR) 7-37
Port Direction Register C (PRRC) 7-37
Port Direction Register D (PRRD) 7-37
prescale divider 7-16
programming model 7-14
receive data interrupt request 7-28
Receive Data Register (RX) 7-14
Receive Shift Register 7-29
receive shift register clock output 7-4
Receive Slot Mask Register (RSM)
programming sheet B-28
Receive Slot Mask Registers (RSMA and
,
RSMB) 7-14
7-35
reset 7-6
RX clock 7-11
RX frame sync 7-11
RX frame sync pulses active 7-11
select source of clock signal 7-22
Serial Clock (SCK), ESSI 7-3
Serial Control 0 (SC00 and SC10) 7-4
Serial Control 1 (SC01 and SC11) 7-4
Serial Control 2 (SC02 and SC12) 7-6
Serial Input Flag (IF0) 7-4
Serial Output Flag 0 (OF0) bit 7-4
Serial Output Flags (OF0–OF1) 7-18
Serial Receive Data (SRD) 7-3
Serial Transmit Data (STD) 7-3
SPI protocol 7-2
Synchronous mode 7-4
Synchronous Serial Interface Status Register
,
(SSISR) 7-14
7-28
bit definitions 7-28
Receive Data Register Full (RDF) 7-28
Receiver Frame Sync Flag (RFS) 7-29
Index-4
,
,
7-10
7-21
,
,
7-20
7-21
,
,
,
7-15
7-20
7-21
,
7-21
,
7-36
,
7-30
,
,
7-11
7-13
DSP56303 User's Manual
Receiver Overrun Error Flag (ROE) 7-28
Serial Input Flag 0 (IF0) 7-29
Serial Input Flag 1 (IF1) 7-29
Transmit Data Register Empty (TDE) 7-28
Transmit Frame Sync Flag (TFS) 7-29
Transmitter Underrun Error Flag (TUE) 7-28
Synchronous/Asynchronous (SYN) bit 7-11
Time Slot Register (TSR) 7-8
Transmit Data Registers (TX0–TX2) 7-14
Transmit Enable (TE) 7-18
Transmit Shift Registers 7-30
Transmit Slot Mask Register (TSM)
programming sheet B-28
Transmit Slot Mask Registers (TSMA and
,
TSMB) 7-14
7-33
TX clock 7-11
variable prescaler 7-16
word length frame sync 7-12
word length frame sync timing 7-12
EOM byte 4-15
ESSI0 Interrupt Priority Level (S0L) bits 4-19
ESSI1 Interrupt Priority Level (S1L) bits 4-19
expansion memory 3-1
Extended Mode Register (EMR) 4-10
Arithmetic Saturation Mode (SM) 4-10
Cache Enable (CE) 4-11
Core Priority (CP) 4-10
DO FOREVER (FV) Flag 4-11
Rounding Mode (RM) 4-10
Sixteen-Bit Arithmetic Mode (SA) 4-11
Extension (E) bit 4-14
external address bus 2-6
,
external bus control 2-6
2-7
External Bus Disable (EBD) bit 4-18
external data bus 2-6
External Memory Expansion Port 2-6
F
frame rate divider 7-10
Frame Rate Divider Control (DC) bits 7-16
frame sync
generator 7-17
length 7-12
selection 7-11
,
,
signal 7-7
7-10
7-18
Frame Sync Length (FSL) bits 7-22
Frame Sync Polarity (FSP) bit 7-22
Frame Sync Relative Timing (FSR) bit 7-22
Framing Error Flag (FE) bit 8-17
G
general-purpose flags for host-DSP communication 6-7
,
7-33
,
7-33
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