Host Port Control Register (Hpcr); Host Port Control Register (Hpcr) Bit Definitions - Motorola DSP56303 User Manual

DSP Core Programming Model
6.6.6

Host Port Control Register (HPCR)

The HPCR is a read/write control register that controls the HI08 operating mode. HPCR bit
initialization values are discussed in Section 6.6.9, DSP-Side Registers After Reset, on page
6-22. Hardware and software reset clear the HPCR bits.
15 14 13 12
HAP HRP HCSP HDDS HMUX HASP HDSP HROD
—Reserved bit, read as 0; write to 0 for future compatibility.
Figure 6-12. Host Port Control Register (HPCR) (X:$FFFFC4)
Note: To assure proper operation of the DSP56303, the HPCR bits HAP, HRP, HCSP,
HDDS, HMUX, HASP, HDSP, HROD, HAEN, and HREN should be changed
only if HEN is cleared. Similarly, the HPCR bits HAP, HRP, HCSP, HDDS,
HMUX, HASP, HDSP, HROD, HAEN, HREN, HCSEN, HA9EN, and HA8EN
should not be set when HEN is set nor at the time HEN is set.
Table 6-12. Host Port Control Register (HPCR) Bit Definitions
Bit Number Bit Name
15 HAP
14 HRP
13 HCSP
6-18
11 10 9 8
Reset Value
0 Host Acknowledge Polarity
If HAP is cleared, the host acknowledge (HACK) signal is configured as an
active low input. The HI08 drives the contents of the IVR onto the host bus
when the HACK signal is low. If the HAP bit is set, the HACK signal is
configured as an active high input. The HI08 outputs the contents of the
IVR when the HACK signal is high.
0 Host Request Polarity
Controls the polarity of the host request signals. In single host request
mode (that is, when HDRQ is cleared in the ICR), if HRP is cleared and
host requests are enabled (that is, if HREN is set and HEN is set), then
the HREQ signal is an active low output. If HRP is set and host requests
are enabled, the HREQ signal is an active high output. In the double host
request mode (that is, when HDRQ is set in the ICR), if HRP is cleared
and host requests are enabled (that is, if HREN is set and HEN is set),
then the HTRQ and HRRQ signals are active low outputs. If HRP is set
and host requests are enabled, the HTRQ and HRRQ signals are active
high outputs.
0 Host Chip Select Polarity
If the HCSP bit is cleared, the host chip select (HCS) signal is configured
as an active low input and the HI08 is selected when the HCS signal is
low. If the HCSP signal is set, HCS is configured as an active high input
and the HI08 is selected when the HCS signal is high.
DSP56303 User's Manual
7 6 5 4
HEN HAEN HREN HCSEN HA9EN HA8EN HGEN
Description
3 2 1 0