Pulse Width Modulation (Pwm, Mode 7) - Motorola DSP56303 User Manual

9.3.3

Pulse Width Modulation (PWM, Mode 7)

Bit Settings
TC3 TC2 TC1
0 1 1
In Mode 7, the timer generates periodic pulses of a preset width. When the counter equals the
value in the TCPR, the
counter are placed into the TCR. If the TCSR[TCIE] bit is set, a compare interrupt is
generated. The counter continues to increment on each timer clock.
If counter overflow occurs, the
overflow interrupt is generated if the TCSR[TOIE] bit is set. If the TCSR[TRM] bit is set, the
counter is loaded with the TLR value on the next timer clock and the count resumes. If the
TCSR[TRM] bit is cleared, the counter continues to increment on each timer clock. This
process repeats until the timer is disabled.
When the TCSR[TE] bit is set and the counter starts, the
On each subsequent toggle of the
example, if the INV bit is set, the
bit is cleared, the
TIO
The value of the TLR determines the output period ($FFFFFF TLR + 1). The timer counter
increments the initial TLR value and toggles the
$FFFFFF. The duty cycle of the
value in the TLR increments to a value equal to the value in the TCPR, the
toggled. The duty cycle is equal to ($FFFFFF – TCPR) divided by ($FFFFFF TLR + 1). For
a 50 percent duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1)/2.
Note: The value in TCPR must be greater than the value in TLR.
TC0 Mode
1 7 Pulse width modulation
output signal is toggled and TCSR[TCF] is set. The contents of the
TIO
output signal is toggled, TCSR[TOF] is set, and an
TIO
signal, the polarity of the
TIO
signal generates the following signal: 1010. If the INV
TIO
signal generates the following signal: 0101.
signal is determined by the value in the TCPR. When the
TIO
Triple Timer Module
Mode Characteristics
Name Function
PWM
signal assumes the value of INV.
TIO
TIO
signal when the counter value exceeds
TIO
Operating Modes
TIO Clock
Output Internal
signal is reversed. For
signal is
TIO
9-19