Xilinx VC709 User Manual page 8

Virtex-7 fpga
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Chapter 1: VC709 Evaluation Board Features
X-Ref Target - Figure 1-2
Round callout references a component
00
on the front side of the board.
13
4
23
15
5
12
11
Table 1-1: VC709 Board Component Descriptions
Reference
Callout
Designator
U1
Virtex-7 FPGA
1
J1, J3
Two DDR3 SODIMM memories (4 GB each)
2
3
U3
BPI parallel NOR flash memory (1 Gb)
4
U26
USB JTAG interface (micro-B USB connector)
5
System clock, 200 MHz, LVDS (back side of
U51
board)
2
I
C programmable user clock LVDS,
6
U34
156.250 MHz default frequency (back side of
board)
J31, J32
User SMA clock
7
J25, J26
GTH transceiver SMA reference clock
8
9
U24
Jitter-attenuated clock (back side of board)
10
U1
GTH transceiver Quad 111–Quad 119
11
P1
PCI Express connector
12
P2–P5
4 X SFP/SFP+ module connector (I²C 0x50)
8
22
6
1
2
10
20
8
Figure 1-2: VC709 Board Component Locations
Component Description
www.xilinx.com
Square callout references a component
00
on the back side of the board.
3
19
18
27
2
7
9
14
Notes
XC7VX690T-2FFG1761CES
Micron MT8KTF51264HZ-1G9E1
Micron/Numonyx
PC28F00AG18FE
Digilent USB JTAG module
SiTime
SIT9102-243N25E200.0000
Silicon Labs
SI570BAB0000544DG (I²C 0x5D)
Rosenberger 32K10K-400L5
Rosenberger 32K10K-400L5
Silicon Labs SI5324C-C-GM
Embedded within FPGA U1
8-lane card edge connector
Molex 74441-0010
24
16
25
21
26
26
17
UG887_c1_02_082612
Schematic
0381499
Page
Number
10, 14
24
5
3
3
3
30
4
30, 36–38
35
31–35
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013

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