Xadc Analog-To-Digital Converter - Xilinx VC709 User Manual

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Table Of Contents

Table of Contents

FPGA Cooling Fan Operation

The FPGA cooling fan control circuit has its PWM signal wired to a dual-use FPGA

bank 15 pin BA37. After configuration, this pin is expected to be toggled by user-provided

fan speed control IP to control fan speed. The fan tachometer feedback signal is wired to

FPGA bank 15 pin BB37.

FPGA U1 pin BA37 is alternately an unused BPI flash memory address pin (A28). During

FPGA configuration in BPI mode, the BPI flash memory address lines are driven. The BA37

pin is held low during BPI configuration and thus the fan PWM signal is not active and the

cooling fan is off during the FPGA BPI configuration process.

After configuration is complete, the dual-use FPGA pin BA37 is available for use by

user-provided fan speed control IP. If no IP is implemented, this pin should be driven High

or placed into hi-Z so pull-up resistor R198 can pull SM_FAN_PWM high to turn the fan

on.

More information about the power system components used by the VC709 board is

available from the Texas Instruments digital power website at

www.ti.com/ww/en/analog/digital-power/index.html.

Documentation describing PMBus programming for the UCD9248 digital power controller

is available at www.ti.com/fusiondocs.

Note:

moderate to high current levels (due to a customer design) might generate substantial heat that can

result in unexpected power module shutdowns from over-temperature conditions. This then turns off

the FPGA on the development board. Refer to the VC709 board master answer record

www.xilinx.com/support/answers/51901.htm