UP1500 User's Manual
2.4.6
Physical S2K Length
2.4.7
Outclk Delay Enable
2.4.8
CPU Div 0
UP1500 800-A1
CPU 0 physical S2K length is encoded using Switches 2 and 3 of SW3.
EV6 / K7 Outclk delay is enabled using Switch 4 of SW3.
Clock divider from CPU 0 is selected using Switches 5, 6, 7 and 8 of SW3.
Chapter 2 System Configuration
2-8