Fpga Emcc Clock - Xilinx VC709 User Manual

One possible I/O standard for the FPGA design clock input is:
3.
X-Ref Target - Figure 1-12

FPGA EMCC Clock

Note:
The VC709 board has a LVCMOS 80 MHz oscillator (U40) soldered onto the board and
wired to the FPGA EMCCLK clock input pin AP37 on bank 14. This 80 MHz single-ended
signal is named FPGA_EMCCLK.
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The FPGA EMCC external configuration clock circuit is shown in
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
NET "sysclk_233_p" LOC = "AY18" | IOSTANDARD = DIFF_SSTL15_DCI | #Bank
32 MRCC input
NET "sysclk_233_n" LOC = "AY17" | IOSTANDARD = DIFF_SSTL15_DCI | #Diff.
Rterm R43 DNP
For more details, see the Si Time
in Figure 1-12.
Figure 1-12: Memory Clock Source
Figure 1-2 callout for this clock.
There is no
Oscillator: Si Time SIT8103AC-23-18E-80.0000Y
PPM frequency jitter: 50 ppm
Single-ended 1.8V LVCMOS output
www.xilinx.com
SiT9122 data sheet. The system clock circuit is shown
Feature Descriptions
UG887_c1_12_011013
Figure 1-13.
31