Xilinx VC709 User Manual page 10

Chapter 1: VC709 Evaluation Board Features
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Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in
4, and 5 respectively as shown in
Note:
Evaluation Kit Master Answer Record (AR
X-Ref Target - Figure 1-3
The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on. See
Configuration Options, page 63
Table 1-2: VC709 Board FPGA Configuration Modes
For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide
(UG470)
I/O Voltage Rails
There are 17 I/O banks available on the Virtex-7 device. Fourteen I/O banks are available
on the VC709 board, and banks 12, 16, and 18 are not used. The voltages applied to the
FPGA I/O banks used by the VC709 board are listed in
Table 1-3: I/O Voltage Rails
10
JTAG using a type-A to micro-B USB cable for connecting the host PC to the VC709
board configuration port
Table 1-2. The mode switches M2, M1, and M0 are on SW11 positions 3,
To determine the FPGA type resident on the VC709 board, see the
ON Position = 1
SW13 DIP Switch
Configuration Mode
Settings (M[2:0])
Master BPI
JTAG
[Ref 2].
FPGA (U1) Bank
Bank 0
Bank 12
Bank 13
Bank 14
Bank 15
Bank 16
Bank 17
Bank 18
www.xilinx.com
Figure 1-3.
51901).
1 2 3 4 5
Figure 1-3: SW11 Default Settings
for detailed information about the mode switch SW11.
Bus Width
010
101
Power Supply Rail Net Name
VCC1V8_FPGA
NOT USED
VCC1V8_FPGA
VCC1V8_FPGA
VCC1V8_FPGA
NOT USED
VCC1V8_FPGA
NOT USED
Virtex-7 VC709
OFF Position = 0
UG887_c1_03_083112
CCLK Direction
x8, x16 Output
x1 Not applicable
Table 1-3.
Voltage
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014