Revision History - Xilinx VC709 User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
02/04/2013 1.0
06/04/2013 1.1
01/07/2014 1.2
03/11/2014 1.2.1
VC709 Evaluation Board
Initial Xilinx release.
Changed XC7VX690T-2FFG1761CES to XC7VX690T-2FFG1761C throughout the
document. Changed SiT9122 to SiT9102. The data rate in
page 19 changed from 40 MHz to 80 MHz. Added items 28 and 29 to the board
photograph in Figure 1-2. FPGA EMCC clock information was added to
Table 1-8, Figure 1-13, and
description for RED changed. Replaced
Flash Address Switch. Enhanced section
information in FMC_VADJ Voltage, page
Configuration Circuit. Replaced
Listing. Updated References, page
Revised the content of Table 1-16, page
FMC1_HPC_LA29_N, page 55
references in Appendix F, Additional Resources
documents throughout document to conform to latest linking style convention. Added
caution note about power connections to J18 on the VC709 board on
link under Declaration of Conformity in Appendix G
PDF instead of XTP251, the list of Certificates of Conformity.
Tech Pubs edit. Technical content not affected.
www.xilinx.com
Revision
FPGA EMCC Clock, page
Figure 1-22 Configuration Mode and Upper Linear
Switches, page
59. Updated
Appendix C, Master UCF Listing with
97.
43. Revised Table 1-20
to FPGA pin T30 (Was W30). Revised all links and
and revised links to web pages and
Linear BPI Flash Memory,
Table 1-7,
31. In Table 1-18, the DS1
49. Updated part ordering
Figure 1-29 VC709 Board
Master XDC
to correct connection of
page 94. Revised
to point directly at the Certificate
UG887 (v1.2.1) March 11, 2014