Table of Contents
Advertisement
Chapter 1: VC709 Evaluation Board Features
fastest configuration method uses the external 80 MHz oscillator connected to the FPGA
EMCCLK pin.
Multiple bitstreams can be stored in the linear BPI flash. The two most significant address
bits (A25, A24) of the flash memory are connected to DIP switch SW11 positions 1 and 2
respectively, and to the RS1 and RS0 pins of the FPGA. By placing valid XC7VX690T
bitstreams at four different offset addresses in the flash memory, 1 of the 4 bitstreams can
be selected to configure the FPGA by appropriately setting the DIP switch SW11. The
connections between the BPI flash memory and the FPGA are listed in
Table 1-6: BPI Flash Memory Connections to the FPGA
20
FPGA (U1) Pin
Net Name
AJ28
FLASH_A0
AH28
FLASH_A1
AG31
FLASH_A2
AF30
FLASH_A3
AK29
FLASH_A4
AK28
FLASH_A5
AG29
FLASH_A6
AK30
FLASH_A7
AJ30
FLASH_A8
AH30
FLASH_A9
AH29
FLASH_A10
AL30
FLASH_A11
AL29
FLASH_A12
AN33
FLASH_A13
AM33
FLASH_A14
AM32
FLASH_A15
AV41
FLASH_A16
AU41
FLASH_A17
BA42
FLASH_A18
AU42
FLASH_A19
AT41
FLASH_A20
BA39
FLASH_A21
BA39
FLASH_A22
BB39
FLASH_A23
AW42
FLASH_A24
AW41
FLASH_A25
www.xilinx.com
Table
BPI Flash Memory (U3)
Pin Number
Pin Name
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
B8
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
1-6.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
Advertisement
Table of Contents
