Watchdog Timers; Interrupt Routing And Generation - Motorola PRPMC750 Installation And Use Manual

Processor pmc module
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Functional Description
3

Watchdog Timers

Interrupt Routing and Generation

3-12
clock. For a 66.66 MHz processor bus, the timer frequency would be 8.33
MHz. Refer to the PRPMC750 Programmer's Reference Guide for
additional information and programming details on these timers.
The Hawk ASIC contains two Watchdog timers, WDT1 and WDT2. Each
timer is functionally equivalent but independent. These timers will
continuously decrement until they reach a count of 0 or are reloaded by
software. The time-out period is programmable from 1 microsecond up to
32 minutes. If the timer count reaches 0, a timer output signal will be
asserted. The output of Watchdog Timer 1 is routed to an MPIC interrupt.
The output of Watchdog Timer 2 is logically ORed onboard to provide a
hard reset. The onboard reset logic will provide a minimum 140
millisecond hard reset when the Watchdog Timer 2 output is asserted.
Following a device reset, WDT1 is enabled with a default time-out of 8
seconds and WDT 2 is enabled with a default time-out of 16 seconds. Each
timer must be disabled or reloaded by software to prevent a time-out.
Software may reload a new timer value or force the timer to reload a
previously loaded value. To disable or load/reload a timer requires a two
step process. Refer to the PRPMC750 Programmer's Reference Guide for
additional timer details. PPCBug disables these timers during
initialization.
External interrupts routed to the Hawk MPIC include the four PCI
interrupts INTA#-INTD#, four host board interrupts from PMC connector
P14, the UART interrupt, and the output from Watchdog Timer 1. The
PrPMC750 has the ability to generate any one of the PCI interrupts
INTA#-INTD# by asserting the Processor 1 interrupt output from MPIC.
The desired PCI interrupt is selected by programming the PCI Interrupt
Select register in the System Register space. Refer to the PrPMC750
Programming Model section for the register description and interrupt
assignments.
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