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Functional Description
General Description
3
Block Diagram
MPC750 Processor
3-4
The PrPMC750 is a processor PMC module based on Motorola's
PowerPlus II architecture. It consists of the MPC750 processor and L2
backside cache, the Hawk System Memory Controller (SMC)/PCI Host
Bridge (PHB) ASIC, 8MB of FLASH memory, 32MB to 128MB of ECC-
protected SDRAM on board with memory expansion capability, and a
debug serial port.
The PrPMC750 module interfaces to the host board PCI bus via the PMC
P11, P12, and P13 connectors, which provides a 64-bit PCI interface
between the host board and the PrPMC750. The PrPMC750 module draws
+5V and +3.3V through the PMC connectors. The onboard Processor Core
Power Supply derives the core voltage from the +5V power. The clock
generator derives all of the required onboard clocks from the PCI clock
input on P11.
The PrPMC750 module has a 2mm header onboard to support module
debug. This header provides the interface to the debug serial RS-232 port
and an interface to the MPC750 processor JTAG/COP port.
The PrPMC750 module can function as a system controller (Monarch) for
the host board or as a slave processor (Non-monarch) PMC, depending on
the state of the MONARCH# signal from the PMC connector. When
configured as the Monarch, the PrPMC750 will enumerate the PCI bus as
well as monitor and service the four PCI interrupts.
The block diagram for the PrPMC750 module is shown in the figure on the
next page.
Figure 3-1
is a block diagram of the PrPMC750's overall architecture.
The PrPMC750 can be ordered with a 233 MHz or a 350 MHz PowerPC
MPC750 processor chip.
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