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Processor 1 interrupt output from MPIC. Refer to the PRPMC750
Programmer's Reference Guide (PRPMC750A/PG) for additional
information and programming details.
FLASH Memory
The PrPMC750 supports two banks of FLASH memory. Bank A is
onboard FLASH while Bank B is optional FLASH located on the carrier
board and accessed through the PMC P14 connector.
Onboard Bank A FLASH
The PrPMC750 contains one bank of 16-bit FLASH memory onboard.
Bank A consists of two AMD (AM29DL323C) 3.3 volt, FBGA devices
configured to operate in byte-wide mode. The total size of the Bank A
FLASH is 8Mbytes.
Optional Bank B FLASH
The signal interface for the Hawk ROM/FLASH Bank B, with multiplexed
address bus, is routed to the PMC P14 connector to support an optional 16-
bit FLASH bank on the carrier board. The Hawk ASIC will support up to
64 Mbytes of FLASH on Bank B. Device loading may restrict this size to
less than 64 Mbytes. The reset vector may be sourced by either Bank A or
Bank B depending on the state of Hawk rom_b_rv control bit. When the
rom_b_rv bit is cleared, address range FFF00000-FFFFFFFF maps to
Bank A. When rom_b_rv bit is set, it maps to Bank B. The default state
uses Bank A for the reset vector. Bank B may be selected by connecting
the BANKB_SEL pin on P14 to 3.3V.
ECC Memory
The PrPMC750 supports one bank of ECC SDRAM onboard and up to
four additional banks of SDRAM on an optional memory mezzanine.
http://www.motorola.com/computer/literature
Block Diagram
3
3-7
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