Operation Of Delay Interrupt Generation Module - Fujitsu MB90480 Series Hardware Manual

CHAPTER 3 INTERRUPT

3.11.1 Operation of Delay Interrupt Generation Module

If CPU writes "1" to the relevant DIRR bit with software, the request latch in the delay
interrupt generation module is set to generate an interrupt request to the interrupt
controller.
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Operation of delay interrupt generation module
If CPU writes "1" to the relevant DIRR bit with software, the request latch in the delay interrupt
generation module is set to generate an interrupt request to the interrupt controller. If other
interrupt requests have a priority lower than this interrupt or there are no other interrupt
requests, the interrupt controller generates an interrupt to the F
16LX CPU compares the interrupt request with the ILM bit in the internal CCR register, and if
the request level is higher than that of the ILM bit, the hardware interrupt processing micro-
program starts immediately after the instruction currently being executed is completed. As a
result, the interrupt routine for this interrupt is executed. By writing "0" to the relevant DDIR bit
within the interrupt processing routine, this interrupt factor is cleared and the task is switched.
The above operation flow is illustrated in the Figure 3.11-2.
Figure 3.11-2 Operation of delay interrupt generation module
Delay interrupt originate module
DIRR
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Notes on using delay interrupt generation module (delay interrupt request latch)
This latch is set by writing "1" to the relevant DIRR bit, and cleared by writing "0" to the same
bit. Be sure to create software so that a factor is cleared in the interrupt processing routine.
Otherwise, interrupt processing starts soon after the system returns from interrupt factor
processing.
94
Interrupt controller
Other
request
ICR
YY
ICR
XX
2
MC-16LX CPU. The F
2
F MC-16LX CPU
ICR
XX
CMP
ICR
XX
NTA
2
MC-
CMP