Free-Running Timer - Fujitsu MB90480 Series Hardware Manual

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER

12.3.1 Free-running timer

This section shows the configuration and explains the functions of free-running timer
registers.
■
List of free-running timer registers
Figure 12.3-4 shows a list of the free-running timer registers.
000067
H
000066
H
000063
H
000062
H
000065
H
000064
H
R/W : Readable/Writable
■
Compare clear register (CPCLR)
Figure 12.3-5 shows the bit configuration of the compare clear register (CPCLR).
Figure 12.3-5 Bit configuration of the compare clear register (CPCLR)
000067 CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXX
000066 CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXX
R/W : Readable/Writable
The compare clear register (CPCLR) is a 16-bit length compare register used to make a
comparison with the free-running timer. An initial value of a register is undefined. Therefore, set
the initial value, then allow the interrupt operation. This register requires word access.
When the MODE bit of the timer counter control status register (TCCS) is set to "1", the free-
running timer value is initialized to "0000
free-running timer. When this register value matches the value of the free-running timer, a
compare clear interrupt flag is set. When the compare interrupt flag is set to "1", an interrupt
request issues to the CPU at allowing the interrupt operation.
224
Figure 12.3-4 List of free-running timer registers
15 14 13 12
CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXX
7 6 5 4
CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXX
15 14 13 12
T15 T14 T13 T12
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000
7 6 5 4
T07 T06 T05 T04
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000
15 14 13 12
ECKE - - MSI2 MSI1 MSI0 ICLR ICRE
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 0 - - 00000
7 6 5 4
IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Timer counter control/status register
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000
15 14 13 12
7 6 5 4
11 10 9 8
3 2 1 0
11 10 9 8
T11 T10 T09 T08
3 2 1 0
T03 T02 T01 T00
11 10 9 8
3 2 1 0
11 10 9 8
3 2 1 0
" at matching this register value and the value of the
H
CPCLR
Compare clear register
B
CPCLR
Compare clear register
B
TCDT
Timer counter data register
B
TCDT
Timer counter data register
B
TCCS
Timer counter control/status register
B
TCCS
B
CPCLR
Compare clear register
CPCLR
Compare clear register
B
B