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CHAPTER 7 MODE SETTING
7.3
Mode Data
Mode data stored at address FFFFDF
after the reset sequence. Mode data is read and stored in the CPU automatically by
mode fetching.
■
Mode data
During the reset sequence, mode data at address FFFFDF
CPU core. The CPU uses this mode data to set the memory access mode. The contents of the
mode register can be changed only by the reset sequence. Furthermore, mode data settings
become valid only after the reset sequence. The configuration of mode data is shown in the
figure below.
■
Setting bits of different modes (S1, S0)
Bits S1 and S0 specify the bus mode and access mode that is set after completion of the reset
sequence.
Table 7.3-1 lists the contents of the settings for bits S1 and S0.
Table 7.3-1 Contents of bit S1 and S0 settings
S1
0
0
1
1
156
in memory specifies the operation immediately
H
7
Mode data
M1
Bus mode
setting bits
S0
0
External data bus 8-bit mode
1
External data bus 16-bit mode
0
External data bus 8-bit mode
1
External data bus 16-bit mode
H
6
5
4
3
M0
0
S1
S0
Setting bits
Function expansion
of different
modes
Functions
Address data bus multiplex
Address data bus non-multiplex
is sent to the mode register in the
2
1
0
0
0
0
bits
(reserved area)
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