Μdmac Processing Procedure - Fujitsu MB90480 Series Hardware Manual

μDMAC Processing Procedure
3.6.3
If an interrupt request is generated by a peripheral resource (I/O) and the
corresponding μDMAC enable register (DER) has a setting of DMA start, then a DMA
transfer is performed. If a data transfer ends at the specified count, an interrupt
request is output to the interrupt controller.
μDMAC processing procedure
■
Figure 3.6-7 shows a simple μDMAC processing procedure.
Software processing
Start
Setting up of system stack area
Initial setup of peripheral function
Setup of interrupt control
register (ICR)
Initial setup of μDMAC controller
Execution of user program
(jumps to the interrupt routine)
Processing interrupt
Processing end
ENx : Bit to which DMA enable register corresponds
DTEx : Bit to which DMA status register corresponds
STPx : Bit to which DMA stop status register corresponds
: Output interrupt request to interrupt controller
Figure 3.6-7 μDMAC processing procedure
(generate interrupt)
NO
NO
(DBAP)
NO
BF= 0
YES
NO
BW = 1
YES
NO
BYTEL = 0
NO
YES
BAP = BAP+2
STPx = 1
ENx = 0
NO
generate
other interrupt
Hardware processing
ENx=1
of ch concerned
YES
STOP request and SE=1
YES
DMA transfer
(DIOA)
NO
IF= 0
BW = 1
BYTEL = 0
DCT = 0
YES YES
IOA = IOA+2
BAP = BAP+1
NO
DCT = 0
YES
DTEx = 1
YES
CHAPTER 3 INTERRUPT
YES
NO
YES
NO
NO
DCT = 0
YES
IOA = IOA+1
YES
generate
interrupt
NO
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