Configuration Of 8/16-Bit Up/Down Counter/Timer - Fujitsu MB90480 Series Hardware Manual

13.2

Configuration of 8/16-bit Up/Down Counter/Timer

The 8-bit up/down counter/timer has two channels and consists of three event input
pins, one 8-bit up/down count, and one 8-bit reload/compare register per channel.
Also, one of two 8-bit up/down counter/timer channels can be used as the 16-bit up/
down counter/timer. (When using as the 16-bit up/down counter/timer, the register of
ch.0 is valid.)
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Block diagram of 8/16-bit up/down counter/timer
Figure 13.2-1 and Figure 13.2-2 are block diagrams of the 8/16-bit up/down counter/timer.
Figure 13.2-1 Block diagram of 8/16-bit up/down counter/timer (channel 0)
CGE1
Edge/level
ZIN0
detected
AIN0
Up/down count
clock selection
BIN0
Prescaler
CLKS
8 bits
CGE0 CGSC
CTUT
UCRE
UDCC
CES1 CES0
CMS1 CMS0
UDMS
UDF1 UDF0 CDCF CFIE
CSTR
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
Data bus
RCR0 (reload/compare register 0)
Reload
control
RLDE
Counter clear
8 bits
UDCR0 (up/down count register 0)
Count clock
CITE UDIE
Interrupt
output
Carry
CMPF
UDFF OVFF
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